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SNAA345 December 2020 LMK5C33216

Trademarks
1 Introduction
2 Wander Generation
3 Wander Transfer
1. 3.1 Transfer Function of the PLL for Option 1 and Option 2
2. 3.2 Wander Transfer TDEV G.8262 Option 2
4 Wander Tolerance
1. 4.1 Wander Tolerance G.8262 Option 1
2. 4.2 Wander Tolerance G.8262 Option 2
5 Jitter Tolerance
1. 5.1 Jitter Tolerance G.8262 Option 1 and Option 2
6 Phase Transient Generation
7 Holdover
1. 7.1 Holdover G.8262 Option 1
2. 7.2 Holdover G.8262 Option 2
8 Free-Run Accuracy
1. 8.1 Free-Run Accuracy G.8262 Option 1 and Option 2
9 Pull-In and Hold-In
1. 9.1 Pull-In Range G.8262 Option 1 and Option 2
10Conclusion
11References

7.1 Holdover G.8262 Option 1

To meet this specification, a PLL in holdover must meet the requirements shown in figure 13 in the G.8262 specification. The procedure for this test is that the LMK5C33216 DUT will lock to IN0, which contains a valid input clock. Then the input is switched to IN1, which contains no valid input, thereby causing the device to enter holdover and remain in holdover for the remainder of the test. The LMK5C33216 device was set up in with a 10-Hz loop bandwidth and forced into holdover. The LMK5C33216 met this specification. The TIE plot shown in Figure 7-1 demonstrates compliance to the standard in green.

Figure 7-1 Holdover Option 1 Result