For this test, the device is forced into holdover for 15 seconds by performing a manual switch from a valid active clock input (IN0) to another input with no valid signal (IN1), then the holdover state is exited by manually switching back to the valid active clock input. The test is completed after an entry into holdover and exit from holdover has taken place within 15 seconds. The output phase variation, relative to the input reference before it was lost, is bounded by the following requirements.

The phase error must not exceed ∆t + 5 × 10^-8 × S seconds over any period S up to 15 seconds. ∆t represents two phase jumps that may occur during the transition into and out of holdover state which both must not exceed 120 ns with a temporary frequency offset of no more than 7.5 ppm. The resultant overall requirements is summarized in green in Figure 6-2 (Figure 12 in the G.8262 specification). This figure is intended to depict the worst-case phase movement attributable to an EEC reference clock switch.

The LMK5C33216 passed the requirements for short-term phase transient response. No significant phase hits were observed during holdover entry and exit using LMK5C33216.

Figure 6-2 Short-Term Phase Transient Result