This section highlights the ADC SNR performance of the AFE7950EVM analog front end evaluation module when clocked by an SMA100B versus the cascaded LMX1204 board.

The AFE7950 is a 4T6R AFE containing four digital to analog converters (DAC) and six analog to digital converters. The input clock is 11,796.48 MHz which is suitable for X-band frequency of operation.

The sample clock of the ADC of 2949.12 MHz is derived from the input clock divided by 4. The receiver operates in a decimate by 12 mode so that the output data rate is 245.76 MSPS. The internal numerically controlled oscillator (NCO) is set to 20 MHz below the center of each RF band so that the baseband tone falls at 20 MHz.

Figure 2-9 plots SNR performance from 8 GHz to 11 GHz in 500 MHz steps. Each input frequency is filtered to reduce the noise and harmonics of the input source. The EVM requires a high clock drive level of around 7 to 15 dBm near 12 GHz due to on-board losses. The LMX1204 output drive is limited to roughly 1 dBm at 12 GHz. The clock output is increased with a Qorvo power amplifier (P/N: CMD158) to 16 dBm followed by a 1 dB pad (to further improve impedance matching) to get to the optimum input level for the AFE7950EVM. The signal generator is set such that the output power matches the measured output power of the cascaded LMX1204 (–0.88 dBm) prior to the amplifier and pad. The amplifier and pad remain in the signal chain for the SMA100B measurements. On average, the SNR is degraded by only 0.19 dB.