SNAS348G May   2006  – April 2016 DAC124S085

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Section
      2. 8.3.2 Output Amplifiers
      3. 8.3.3 Reference Voltage
      4. 8.3.4 Power-On Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
      2. 8.5.2 Input Shift Register
      3. 8.5.3 DSP or Microprocessor Interfacing
        1. 8.5.3.1 ADSP-2101 or ADSP2103 Interfacing
        2. 8.5.3.2 80C51 or 80L51 Interface
        3. 8.5.3.3 68HC11 Interface
      4. 8.5.4 Microwire Interface
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Bipolar Operation
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Using References as Power Supplies
      1. 10.1.1 LM4132
      2. 10.1.2 LM4050
      3. 10.1.3 LP3985
      4. 10.1.4 LP2980
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

6 Pin Configuration and Functions

DGS Package
10-Pin VSSOP
Top View
DSC Package
10-Pin WSON
Top View

Pin Functions

PIN TYPE(1) DESCRIPTION
NO. NAME
1 VA S Power supply input. Must be decoupled to GND.
2 VOUTA O Channel A analog output voltage.
3 VOUTB O Channel B analog output voltage.
4 VOUTC O Channel C analog output voltage.
5 VOUTD O Channel D analog output voltage.
6 GND G Ground reference for all on-chip circuitry.
7 VREFIN I Unbuffered reference voltage shared by all channels. Must be decoupled to GND.
8 DIN I Serial data input. Data is clocked into the 16-bit shift register on the falling edges of SCLK after the fall of SYNC.
9 SYNC I Frame synchronization input for the data input. When this pin goes low, it enables the input shift register and data is transferred on the falling edges of SCLK. The DAC is updated on the 16th clock cycle unless SYNC is brought high before the 16th clock, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.
10 SCLK I Serial clock input. Data is clocked into the input shift register on the falling edges of this pin.
11 PAD
(WSON only)		 G Exposed die attach pad can be connected to ground or left floating. Soldering the pad to the PCB offers optimal thermal performance and enhances package self-alignment during reflow.
(1) G = Ground, I = Input, O = Output, and S = Supply
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