SNAS407H August   2007  – April 2015 DAC128S085

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 AC and Timing Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Architecture
      2. 8.3.2 Output Amplifiers
      3. 8.3.3 Reference Voltage
      4. 8.3.4 Serial Interface
      5. 8.3.5 Daisy-Chain Operation
      6. 8.3.6 DAC Input Data Update Mechanism
      7. 8.3.7 Power-On Reset
      8. 8.3.8 Transfer Characteristic
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Modes
    5. 8.5 Programming
      1. 8.5.1 Programming the DAC128S085
        1. 8.5.1.1 Updating DAC Outputs Simultaneously
        2. 8.5.1.2 Updating DAC Outputs Independently
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Using References as Power Supplies
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Specification Definitions
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

6 Pin Configuration and Functions

RGH Package
16-Pin WQFN
(Top View)
DAC128S085 PinOut_RGH-16_SNAS407.gif
PW Package
16-Pin TSSOP
(Top View)
DAC128S085 PinOut_PW-16_SNAS407.gif

Pin Functions

PIN TYPE DESCRIPTION
NAME TSSOP NO. WQFN NO.
DIN 1 15 Digital Input Serial Data Input. Data is clocked into the 16-bit shift register on the falling edges of SCLK after the fall of SYNC.
DOUT 2 16 Digital Output Serial Data Output. DOUT is utilized in daisy chain operation and is connected directly to a DIN pin on another DAC128S085. Data is not available at DOUT unless SYNC remains low for more than 16 SCLK cycles.
GND 10 8 Ground Ground reference for all on-chip circuitry.
SCLK 16 14 Digital Input Serial Clock Input. Data is clocked into the input shift register on the falling edges of this pin.
SYNC 15 13 Digital Input Frame Synchronization Input. When this pin goes low, data is written into the DAC's input shift register on the falling edges of SCLK. After the 16th falling edge of SCLK, a rising edge of SYNC causes the DAC to be updated. If SYNC is brought high before the 15th falling edge of SCLK, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.
VA 7 5 Supply Power supply input. Must be decoupled to GND.
VOUTA 3 1 Analog Output Channel A Analog Output Voltage.
VOUTB 4 2 Analog Output Channel B Analog Output Voltage.
VOUTC 5 3 Analog Output Channel C Analog Output Voltage.
VOUTD 6 4 Analog Output Channel D Analog Output Voltage.
VOUTE 14 12 Analog Output Channel E Analog Output Voltage.
VOUTF 13 11 Analog Output Channel F Analog Output Voltage.
VOUTG 12 10 Analog Output Channel G Analog Output Voltage.
VOUTH 11 9 Analog Output Channel H Analog Output Voltage.
VREF1 8 6 Analog Input Unbuffered reference voltage shared by Channels A, B, C, and D. Must be decoupled to GND.
VREF2 9 7 Analog Input Unbuffered reference voltage shared by Channels E, F, G, and H. Must be decoupled to GND.
PAD
(WQFN only)		 — 17 Ground Exposed die attach pad can be connected to ground or left floating. Soldering the pad to the PCB offers optimal thermal performance and enhances package self-alignment during reflow.
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