SNAS410F May   2008  – July 2016 DAC121S101QML-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DAC121S101QML-SP Electrical Characteristics DC Parameters
    6. 6.6 DAC121S101QML-SP Electrical Characteristics AC and Timing Characteristics
    7. 6.7 DAC121S101QML Electrical Characteristics Radiation Electrical Characteristics
    8. 6.8 DAC121S101QML-SP Electrical Characteristics Operating Life Test Delta Parameters TA at 25°C
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DAC Section
      2. 7.3.2 Resistor String
      3. 7.3.3 Output Amplifier
      4. 7.3.4 Power-On Reset
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Down Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Input Shift Register
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Bipolar Operation
      2. 8.1.2 DSP and Microprocessor Interfacing
        1. 8.1.2.1 ADSP-2101/ADSP2103 Interfacing
        2. 8.1.2.2 80C51/80L51 Interface
        3. 8.1.2.3 68HC11 Interface
        4. 8.1.2.4 Microwire Interface
      3. 8.1.3 Radiation Environments
        1. 8.1.3.1 Total Ionizing Dose
          1. 8.1.3.1.1 DAC121S101WGRQV 5962R0722601VZA
          2. 8.1.3.1.2 DAC121S101WGRLV 5962R0722602VZA
        2. 8.1.3.2 Single Event Latch-Up and Functional Interrupt
        3. 8.1.3.3 Single Event Upset
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 Using References as Power Supplies
      1. 9.1.1 LM4050QML-SP
      2. 9.1.2 LP3985
      3. 9.1.3 LP2980-N
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Specification Definitions
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Engineering Samples

5 Pin Configuration and Functions

NAC Package
10-Pin CFP
Top View
DAC121S101QML-SP 30018001.gif

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
1 VA — Power supply and reference input; must be decoupled to GND
2 N/C — No connect; pin not internally connected to die
3 N/C — No connect; pin not internally connected to die
4 VOUT Output DAC analog output voltage
5 N/C — No connect; pin not internally connected to die
6 N/C — No connect; pin not internally connected to die
7 SYNC Input Frame synchronization input for the data input. When this pin goes low, it enables the input shift register and data is transferred on the falling edges of SCLK. The DAC is updated on the 16th clock cycle unless SYNC is brought high before the 16th clock, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.
8 SCLK Input Serial clock input; data is clocked into the input shift register on the falling edges of this pin.
9 DIN Input Serial data input; data is clocked into the 16-bit shift register on the falling edges of SCLK after the fall of SYNC.
10 GND — Ground reference for all on-chip circuitry
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