米6体育平台手机版

SNAS410F May 2008 – July 2016 DAC121S101QML-SP

PRODUCTION DATA.

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾⁽²⁾

		MIN	MAX	UNIT
Supply voltage, V_A			6.5	V
Voltage on any input pin		−0.3	(V_A + 0.3)	V
Input current at any pin⁽³⁾			10	mA
Maximum output current⁽⁴⁾			10	mA
V_OUT pin in power-down mode			1	mA
Package input current⁽³⁾			20	mA
Power dissipation at T_A = 25°C		See⁽⁵⁾
Maximum junction temperature			175	°C
Lead temperature	CFP package (Soldering 10 Seconds)		260	°C
Package weight (typical)	CFP package		220	mg
Storage temperature, T_stg		−65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are measured with respect to GND = 0 V, unless otherwise specified.

(3) When the input voltage at any pin exceeds the power supplies (that is, less than GND, or greater than V_A), the current at that pin should be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two.

(4) Maximum output current may not exceed 10 mA. At V_DD = 5.5 V the minimum external resistive load can be no less than 550 Ω
(360 Ω at V_DD = 3.6 V).

(5) The absolute maximum junction temperature (T_Jmax) for this device is 175°C. The maximum allowable power dissipation is dictated by T_Jmax, the junction-to-ambient thermal resistance (R_θJA), and the ambient temperature (T_A), and can be calculated using the formula P_DMAX = (T_Jmax − T_A) / R_θJA. The values for maximum power dissipation will be reached only when the device is operated in a severe fault condition (for example, when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions must be avoided.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾⁽²⁾	±5000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) Human body model is 100-pF capacitor discharged through a 1.5-kΩ resistor. Machine model is 220 pF discharged through 0 Ω.

6.3 Recommended Operating Conditions

	MIN	MAX	UNIT
Operating temperature	−55	125	°C
Supply voltage, V_A	2.7	5.5	V
Any input voltage⁽¹⁾	−0.1	(V_A + 0.1)	V
Output load	0	1500	pF
SCLK frequency		20	MHz

(1) The analog inputs are protected as shown below. Input voltage magnitudes up to V_A + 300 mV or to 300 mV below GND will not damage this device. However, errors in the conversion result can occur if any input goes above V_A or below GND by more than 100 mV. For example, if V_A is 2.7-V DC , ensure that –100 mV ≤ input voltages ≤ 2.8-V DC to ensure accurate conversions.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾⁽²⁾		DAC121S101QML-SP	UNIT
		NAC (CFP)
		10 PINS
R_θJA	Junction-to-ambient thermal resistance	214	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	25.7	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

(2) 10-pin CFP Package on 2-layer, 1-oz. PCB

6.5 DAC121S101QML-SP Electrical Characteristics DC Parameters

The following specifications apply for V_A = 2.7 V to 5.5 V, R_L = ∞, C_L = 200 pF to GND, f_SCLK = 20 MHz, input code range 48 to 4047. All limits T_A = 25°C, unless otherwise specified.

PARAMETER		TEST CONDITIONS		NOTES	SUB-GROUPS	MIN	TYP⁽¹⁾	MAX	UNIT
STATIC PERFORMANCE
	Resolution	T_MIN ≤ T_A ≤ T_MAX		See⁽²⁾		12			Bits
	Monotonicity	T_MIN ≤ T_A ≤ T_MAX		See⁽²⁾		12			Bits
INL	Integral non-linearity	Over Decimal codes 48 to 4047			[1, 2, 3]	−8	±2.75	8	LSB
DNL	Differential non-linearity	V_A = 2.7 V to 5.5 V	DNL MAX		[1, 2, 3]		0.21	1	LSB
DNL	Differential non-linearity	V_A = 2.7 V to 5.5 V	DNL MIN		[1, 2, 3]	−0.7	−0.1		LSB
ZE	Zero code error	I_OUT = 0			[1, 2, 3]		2.12	15	mV
FSE	Full-scale error	I_OUT = 0			[1, 2, 3]		−0.04	−1	%FSR
GE	Gain error	All ones Loaded to DAC register			[1, 2, 3]		−0.11	±1	%FSR
ZCED	Zero code error drift			See⁽²⁾			−20		µV/°C
TC GE	Gain error tempco	V_A = 3 V		See⁽²⁾			−0.7		ppm/°C
TC GE	Gain error tempco	V_A = 5 V		See⁽²⁾			−1		ppm/°C
OUTPUT CHARACTERISTICS
^IPD SINK	Vout pin in power-down mode	All PD Modes, T_MIN ≤ T_A ≤ T_MAX		See⁽²⁾				1	mA
	Output voltage range	T_MIN ≤ T_A ≤ T_MAX		See⁽²⁾		0		V_A	V
ZCO	Zero code output	V_A = 3 V, I_OUT = 10 µA			[1, 2, 3]		2	6	mV
		V_A = 3 V, I_OUT = 100 µA			[1, 2, 3]		4	10
		V_A = 5 V, I_OUT = 10 µA			[1, 2, 3]		2	8
		V_A = 5 V, I_OUT = 100 µA			[1, 2, 3]		4	9
FSO	Full-scale output	V_A = 3 V, I_OUT = 10 µA			[1, 2, 3]	2.99	2.997		V
		V_A = 3 V, I_OUT = 100 µA			[1, 2, 3]	2.985	2.991
		V_A = 5 V, I_OUT = 10 µA			[1, 2, 3]	4.985	4.994
		V_A = 5 V, I_OUT = 100 µA			[1, 2, 3]	4.985	4.992
	Maximum load capacitance	R_L = ∞		See⁽²⁾			1500		pF
	Maximum load capacitance	R_L = 2 kΩ		See⁽²⁾			1500		pF
	DC output impedance				[1, 2, 3]		8	16	Ω
LOGIC INPUT
I_IN	Input current				[1, 2, 3]	−200	6	200	nA
V_IL	Input low voltage	V_A = 5 V, T_MIN ≤ T_A ≤ T_MAX			[1, 2, 3]			0.8	V
V_IL	Input low voltage	V_A = 3 V, T_MIN ≤ T_A ≤ T_MAX			[1, 2, 3]			0.5	V
V_IH	Input high voltage	V_A = 5 V, T_MIN ≤ T_A ≤ T_MAX			[1, 2, 3]	2.4			V
V_IH	Input high voltage	V_A = 3 V, T_MIN ≤ T_A ≤ T_MAX			[1, 2, 3]	2.1			V
C_IN	Input capacitance			See⁽²⁾			5		pF
POWER REQUIREMENTS
I_A	Supply current (output unloaded)	Normal Mode 5.5 V f_SCLK = 20 MHz			[1, 2, 3]		216	270	µA
		Normal Mode 3.6 V f_SCLK = 20 MHz			[1, 2, 3]		145	200
		Normal Mode 5.5 V f_SCLK = 10 MHz			[1, 2, 3]		185	230
		Normal Mode 3.6 V f_SCLK = 10 MHz			[1, 2, 3]		132	175
		Normal Mode 5.5 V f_SCLK = 0			[1, 2, 3]		150	190
		Normal Mode 3.6 V f_SCLK = 0			[1, 2, 3]		115	160
		All PD Modes, 5.5 V f_SCLK = 20 MHz			[1, 2, 3]		22	60
		All PD Modes, 3.6 V f_SCLK = 20 MHz			[1, 2, 3]		12	30
		All PD Modes, 5.5 V f_SCLK = 10 MHz			[1, 2, 3]		12	40
		All PD Modes, 3.6 V f_SCLK = 10 MHz			[1, 2, 3]		6	20
		All PD Modes, 5.5 V f_SCLK = 0			[1, 2, 3]		0.006	1
		All PD Modes, 3.6 V f_SCLK = 0			[1, 2, 3]		0.004	1
P_C	Power consumption (output unloaded)	Normal Mode, 5.5 V f_SCLK = 20 MHz			[1, 2, 3]		1.19	1.49	mW
		Normal Mode 3.6 V f_SCLK = 20 MHz			[1, 2, 3]		0.52	0.72
		Normal Mode, 5.5 V f_SCLK = 10 MHz			[1, 2, 3]		1.02	1.27
		Normal Mode 3.6 V f_SCLK = 10 MHz			[1, 2, 3]		0.47	0.63
		Normal Mode, 5.5 V f_SCLK = 0			[1, 2, 3]		0.82	1.05
		Normal Mode 3.6 V f_SCLK = 0			[1, 2, 3]		0.41	0.58
		All PD Modes, 5.5 V f_SCLK = 20 MHz			[1, 2, 3]		0.12	0.33
		All PD Modes, 3.6 V f_SCLK = 20 MHz			[1, 2, 3]		0.07	0.11
		All PD Modes, 5.5 V f_SCLK = 10 MHz			[1, 2, 3]		0.04	0.22
		All PD Modes, 3.6 V f_SCLK = 10 MHz			[1, 2, 3]		0.02	0.08
		All PD Modes, 5.5 V f_SCLK = 0			[1, 2, 3]		0.033	5.5
		All PD Modes, 3.6 V f_SCLK = 0			[1, 2, 3]		0.014	3.6
I_OUT	Power efficiency	I_LOAD = 2 mA		See⁽²⁾			91%
I_A	Power efficiency	I_LOAD = 2 mA		See⁽²⁾			94%

(1) Typical figures are at T_J = 25°C, and represent most likely parametric norms.

(2) This parameter is ensured by design and/or characterization and is not tested in production.

6.6 DAC121S101QML-SP Electrical Characteristics AC and Timing Characteristics

The following specifications apply for V_A = 2.7 V to 5.5 V, R_L = ∞, C_L = 200 pF to GND, f_SCLK = 20 MHz, input code range 48 to 4047. All limits T_A = 25°C, unless otherwise specified.

PARAMETER		TEST CONDITIONS		NOTES	SUB-GROUPS	MIN	TYP⁽¹⁾	MAX	UNIT
f_SCLK	SCLK frequency	(See Figure 31)			[9,10,11]			20	MHz
t_s	Output voltage settling time	FF0 to 00F code change, R_L = ∞	C_L ≤ 200 pF		[9,10,11]		12.5	15	µs
		FF0 to 00F code change, R_L = ∞	C_L = 500 pF		[9,10,11]		12.5	15
		00Fh to FF0h code change, R_L = ∞	C_L ≤ 200 pF		[9,10,11]		12.5	15
		00Fh to FF0h code change, R_L = ∞	C_L = 500 pF		[9,10,11]		12.5	15
SR	Output slew rate			See⁽²⁾			1		V/µs
	Glitch impulse	Code change from 800h to 7FFh		See⁽²⁾			12		nV-sec
	Digital feedthrough			See⁽²⁾			0.5		nV-sec
t_WU	Wake-Up Time	V_A = 5 V		See⁽²⁾			0.65		µs
t_WU	Wake-Up Time	V_A = 3 V		See⁽²⁾			1.1		µs
1/f_SCLK	SCLK cycle time	(See Figure 31)			[9,10,11]	50			ns
t_H	SCLK high time	(See Figure 31)			[9,10,11]	20			ns
t_L	SCLK low time	(See Figure 31)			[9,10,11]	20			ns
t_SUCL	Setup time SYNC to SCLK rising edge	(See Figure 31)			[9,10,11]	0			ns
t_SUD	Data setup time	(See Figure 31)			[9,10,11]	6			ns
t_DHD	Data hold time	(See Figure 31)			[9,10,11]	4.5			ns
t_CS	SCLK fall to rise of SYNC	V_A = 5.5 V (See Figure 31)			[9,10,11]	10			ns
t_CS	SCLK fall to rise of SYNC	V_A = 2.7 V (See Figure 31)			[9,10,11]	18			ns
t_SYNC	SYNC high time	V_A = 5.5 V (See Figure 31)			[9,10,11]	37			ns
t_SYNC	SYNC high time	V_A = 2.7 V (See Figure 31)			[9,10,11]	36			ns

(1) Typical figures are at T_J = 25°C, and represent most likely parametric norms.

(2) This parameter is ensured by design and/or characterization and is not tested in production.

6.7 DAC121S101QML Electrical Characteristics Radiation Electrical Characteristics⁽¹⁾

The following specifications apply for V_A = 2.7 V to 5.5 V, R_L = ∞, C_L = 200 pF to GND, f_SCLK = 20 MHz, input code range 48 to 4047.

PARAMETER		TEST CONDITIONS		SUB-GROUPS	MAX	UNIT
POWER REQUIREMENTS
I_A	Supply current (output unloaded)	Normal Mode f_SCLK = 20 MHz	5.5 V	[1]	325	µA
		Normal Mode f_SCLK = 20 MHz	3.6 V	[1]	250
		Normal Mode f_SCLK = 10 MHz	5.5 V	[1]	300
		Normal Mode f_SCLK = 10 MHz	3.6 V	[1]	225
		Normal Mode f_SCLK = 0	5.5 V	[1]	275
		Normal Mode f_SCLK = 0	3.6 V	[1]	200
		All PD Modes, f_SCLK = 20 MHz	5.5 V	[1]	125
		All PD Modes, f_SCLK = 20 MHz	3.6 V	[1]	100
		All PD Modes, f_SCLK = 10 MHz	5.5 V	[1]	115
		All PD Modes, f_SCLK = 10 MHz	3.6 V	[1]	95
		All PD Modes, f_SCLK = 0	5.5 V	[1]	100
		All PD Modes, f_SCLK = 0	3.6 V	[1]	100

(1) Pre- and post-irradiation limits are identical to those listed in the DAC121S101QML-SP Electrical Characteristics DC Parameters and DAC121S101QML-SP Electrical Characteristics AC and Timing Characteristics tables, except as listed in the Radiation Electrical Characteristics table. When performing post irradiation electrical measurements for any RHA level, T_A = 25°C. See Radiation Environments for dose rate and test conditions.

6.8 DAC121S101QML-SP Electrical Characteristics Operating Life Test Delta Parameters
T_A at 25°C⁽¹⁾

PARAMETER		TEST CONDITIONS	SUB-GROUPS	MAX	UNIT
INL	Integral non-linearity		[1]	±2	LBS
ts	Output voltage settling time		[1]	±5	µA
I_A	Supply current (output unloaded)	Normal Mode, V_A = 5.5 V, f_SCLK = 20 MHz	[1]	±10	µA
		Normal Mode, V_A = 3.6 V, f_SCLK = 20 MHz	[1]	±6
		Normal Mode, V_A = 5.5 V, f_SCLK = 10 MHz	[1]	±10
		Normal Mode, V_A = 3.6 V, f_SCLK = 10 MHz	[1]	±6
		Normal Mode, V_A = 5.5 V, f_SCLK = 0	[1]	±8
		Normal Mode, V_A = 3.6 V, f_SCLK = 0	[1]	±6
		All PD Modes, V_A = 5.5 V, f_SCLK = 20 MHz	[1]	±2
		All PD Modes, V_A = 3.6 V, f_SCLK = 20 MHz	[1]	±1
		All PD Modes, V_A = 5.5 V, f_SCLK = 10 MHz	[1]	±1
		All PD Modes, V_A = 3.6 V, f_SCLK = 10 MHz	[1]	±1
		All PD Modes, V_A = 5.5 V, f_SCLK = 0	[1]	±0.1
		All PD Modes, V_A = 3.6 V, f_SCLK = 0	[1]	±0.1

(1) These parameters are worse case drift. Deltas are performed at room temperature Post OP Life. All other parameters no Deltas are required.

The DAC121S101QML-SP operates over the extended temperature range of –55°C to +125°C.

See Radiation Environments for dose rate environment information.

Table 1. Quality Conformance Inspection⁽¹⁾

SUB-GROUP	DESCRIPTION	TEMP (°C)
1	Static tests at	+25
2	Static tests at	+125
3	Static tests at	–55
4	Dynamic tests at	+25
5	Dynamic tests at	+125
6	Dynamic tests at	–55
7	Functional tests at	+25
8A	Functional tests at	+125
8B	Functional tests at	–55
9	Switching tests at	+25
10	Switching tests at	+125
11	Switching tests at	–55
12	Setting time at	+25
13	Setting time at	+125
14	Setting time at	–55