8.3.1 General Amplifier Function

The LM48560 device is a fully differential, Class H piezo driver for ceramic speakers and haptic actuators. The integrated, high efficiency boost converter dynamically adjusts the amplifier’s supply voltage based on the output signal, increasing headroom and improving efficiency compared to a conventional Class AB driver. The fully differential amplifier takes advantage of the increased headroom and bridge-tied load (BTL) architecture, delivering significantly more voltage than a single-ended amplifier.

8.3.2 Class H Operation

Class H is a modification of another amplifier class (typically Class B or Class AB) to increase efficiency and reduce power dissipation. To decrease power dissipation, Class H uses a tracking power supply that monitors the output signal and adjusts the supply accordingly. When the amplifier output is below 3V_P-P, the nominal boost voltage is 6 V. As the amplifier output increases above 3 V_P-P, the boost voltage tracks the amplifier output as shown in Figure 24. When the amplifier output falls below 3 V_P-P, the boost converter returns to its nominal output voltage. Power dissipation is greatly reduced compared to conventional Class AB drivers.

Figure 24. Class H Operation

8.3.3 Differential Amplifier Explanation

The LM48560 device features a fully differential amplifier. A differential amplifier amplifies the difference between the two input signals. A major benefit of the fully differential amplifier is the improved common mode rejection ratio (CMRR) over single ended input amplifiers. The increased CMRR of the differential amplifier reduces sensitivity to ground offset related noise injection, especially important in noisy systems.

8.3.4 Automatic Level Control (ALC)

The ALC is available in software mode only, and only in boosted mode. In hardware mode ALC is always disabled. The ALC limits the peak output voltage to the programmed value. Consequently, it limits the peak boost voltage, as this is derived from the output voltage. The ALC is continuous, in that it provides a continuous adjustment of the voltage gain to limit the output voltage to the programmed value. The available gain adjustment range is typically 8 dB. When the input amplitude is further increased beyond the ALC attenuation range, the output will again increase. This is illustrated in the Typical Performance Graphs, as seen on the 14 V_PP plot in the Input voltage vs Output Voltage curve. The attack and decay of the ALC is programmed by software and works in conjunction with the external capacitor C_SET. Typically C_SET is 0.1 μF, although it can be changed from 0.1 μF to 4.7 μF to select other ranges of attack and decay time.

8.3.5 Attack Time

Attack time (t_ATK) is the time it takes for the gain to be reduced by 6 dB once the audio signal exceeds the ALC threshold. Fast attack times allow the ALC to react quickly and prevent transients such as symbol crashes from being distorted. However, fast attack times can lead to volume pumping, where the gain reduction and release becomes noticeable, as the ALC cycles quickly. Slower attack times cause the ALC to ignore the fast transients, and instead act upon longer, louder passages. Selecting an attack time that is too slow can lead to increased distortion in the case of the No Clip function, and possible output overload conditions in the case of the Voltage limiter. The attack time is set by a combination of the value of C_SET and the attack time coefficient as given by Equation 1:

Where α_ATK is the attack time coefficient (Table 1) set by bits B4:B3 in the Voltage Limit Control Register. The attack time coefficient allows the user to set a nominal attack time. The internal 20 kΩ resistor is subject to temperature change, and it has tolerance between –11% to +20%.

8.3.6 Release Time

Release time (t_RL) is the time it takes for the gain to return from 6 dB to its normal level once the audio signal returns below the ALC threshold. A fast release time allows the ALC to react quickly to transients, preserving the original dynamics of the audio source. However, similar to a fast attack time, a fast release time contributes to volume pumping. A slow release time reduces the effect of volume pumping. The release time is set by a combination of the value of C_SET and release time coefficient as given by Equation 2:

where α_RL is the release time coefficient (Table 2) set by bits B6:B5 in the No Clip Control Register. The release time coefficient allows the user to set a nominal release time. The internal 20 MΩ is subject to temperature change, and it has tolerance between -11% to +20%.

8.3.7 Boost Converter

The LM48560 device features an integrated boost converter with a dynamic output control. The device monitors the output signal of the amplifier, and adjusts the output voltage of the boost converter to maintain sufficient headroom while improving efficiency.

8.3.8 Gain Setting

The LM48560 device features four internally configured gain settings 0 db, 6 dB, and 30 dB. The device gain is selected through a single pin (GAIN). The gain settings are shown in Table 3.

8.3.9 Shutdown Function

The LM48560 device features a low current shutdown mode. Set SD = GND to disable the amplifier and boost converter and reduce supply current to 0.01 µA.

8.4.1 Software or Hardware Mode

Device operation in hardware or software mode is determined by the state of the SW/HW pin. Connect SW/HW to ground for hardware mode, and connect to V_DD for software mode.

8.4.2 Single-Ended Input Configuration

The LM48560 device is compatible with single-ended sources. When configured for single-ended inputs, input capacitors must be used to block and DC component at the input of the device. Figure 25 shows the typical single-ended applications circuit.

Figure 25. Single-Ended Input Configuration

8.5.1 Read/Write I²C Compatible Interface

The LM48560 device is controlled through an I²C compatible serial interface that consists of a serial data line (SDA) and a serial clock (SCL). The clock line is uni-directional. The data line is bi-directional (open drain). The LM48560 device and the master can communicate at clock rates up to 400 kHz. Figure 1 shows the I²C interface timing diagram. Data on the SDA line must be stable during the HIGH period of SCL. The LM48560 device is a transmit/receive slave-only device, reliant upon the master to generate the SCL signal. Each transmission sequence is framed by a START condition and a STOP condition Figure 2. Each data word, device address and data, transmitted over the bus is 8 bits long and is always followed by an acknowledge pulse Figure 26. The LM48560 device address is 1101111.

8.5.2 Write Sequence

The example write sequence is shown in Figure 26. The START signal, the transition of SDA from HIGH to LOW while SDA is HIGH, is generated, altering all devices on the bus that a device address is being written to the bus.

The 7-bit device address is written to the bus, most significant bit (MSB) first, followed by the R/W bit (R/W = 0 indicating the master is writing to the LM48560 device). The data is latched in on the rising edge of the clock. Each address bit must be stable while SDA is HIGH. After the R/W bit is transmitted, the master device releases SDA, during which time, an acknowledge clock pulse is generated by the slave device. If the LM48560 device receives the correct address, the device pulls the SDA line low, generating and acknowledge bit (ACK).

Once the master device registers the ACK bit, the 8-bit register address word is sent, MSB first. Each data bit should be stable while SCL is HIGH. After the 8-bit register address is sent, the LM48560 device sends another ACK bit. Upon receipt of the acknowledge, the 8-bit register data is sent, MSB first. The register data word is followed by an ACK, upon receipt of which, the master issues a STOP bit, allowing SDA to go high while SDA is high.

Figure 26. Example I²C Write Cycle

8.5.3 Read Sequence

The example read sequence is shown in Figure 27. The START signal, the transition of SDA from HIGH to LOW while SDA is HIGH, is generated, altering all devices on the bus that a device address is being written to the bus.

The 7-bit device address is written to the bus, followed by the R/W = 1 (R/W = 1 indicating the master wants to read data from the LM48560 device). After the R/W bit is transmitted, the master device releases SDA, during which time, an acknowledge clock pulse is generated by the slave device. If the LM48560 device receives the correct address, the device pulls the SDA line low, generating and acknowledge bit (ACK). Once the master device registers the ACK bit, the 8-bit register address word is sent, MSB first, followed by an ACK and selected register data from the LM48560 device. The register data is sent MSB first. Following the acknowledgment of the register data word [7:0], the master issues a STOP bit, allowing SDA to go high while SDA is high.

Figure 27. Example I²C Read Cycle

Table 6. I²C Control Registers

Table 7. Shutdown Control Register

Table 8. No Clip Control Register

Table 9. Gain Control Register