9.3.5.3 Input Clock Switching - Automatic Mode

When CLKin_SEL_MODE is 4 and LOS_EN = 1, the active clock is selected in round-robin order of enabled clock inputs, starting on an input clock switch event. The switching order of the clocks is CLKin0 → CLKin1 → CLKin2 → CLKin0, and so forth.

For a clock input to be eligible to be switched through, it must be enabled using EN_CLKinX. The LOS_TIMEOUT should also be set to a frequency below the input frequency.

To ensure LOS is valid for AC-coupled inputs, the MOS mode must be set for CLKinX and no termination is allowed to be between the pins unless DC-blocked. For example, with an LVDS differential signal into CLKin0, no 100-Ω termination should be placed directly across CLKin0 and CLKin0* pins on the IC side of the AC coupling capacitors. 100 Ω could instead be placed on the transmitter side of the AC coupling capacitors.

Starting Active Clock

When programming this mode, the currently active clock remains active if PLL1 lock detect is high. To ensure a particular clock input is the active clock when starting this mode, program CLKin_SEL_MODE to the manual mode which selects the desired clock input (CLKin0, 1, or 2). Wait for PLL1 to lock PLL1_DLD = 1, then select this mode with CLKin_SEL_MODE = 4.