SNAU249A December   2019  – December 2020 LMK1C1104

 

  1.   Trademarks
  2. 1Features
  3. 2Signal Path and Control Circuitry
  4. 3Getting Started
  5. 4Power-Supply Connections
  6. 5Enabling/Disabling the Outputs
  7. 6Output Clock
  8. 7Bill of Materials
    1. 7.1 REACH Compliance
  9. 8Schematic
  10. 9Revision History

LMK1C1104 Abstract

GUID-20201121-CA0I-8ZHF-NKPB-RVP7LBGD6C06-low.svg Figure 1-1 LMK1C1104EVM

The LMK1C1104 is a high-performance, low additive jitter LVCMOS clock buffer with one LVCMOS input, four LVCMOS outputs, and a global output enable pin.

This evaluation module (EVM) is designed to demonstrate the electrical performance of the LMK1C1104. Throughout this document, the acronym EVM and the phrases evaluation module and evaluation board are synonymous with the LMK1C1104EVM. Figure 8-1 illustrates the LMK1C1104EVM.

The LMK1C1104EVM is equipped with 50-Ω SMA connectors and impedance-controlled 50-Ω microstrip transmission lines for best performance.