SNAU252 June 2020 LMK04832-SP
Table 5 contains descriptions of the inputs and outputs for the evaluation board. Additionally, some applicable TICS Pro programming controls are noted for convenience.
| CONNECTOR NAME | SIGNAL TYPE,
INPUT/OUTPUT |
DESCRIPTION | ||
|---|---|---|---|---|
| Clock Outputs
CLKout0_P(J29), CLKout0_N(J30), CLKout1_P(J16), CLKout1_N(J15), CLKout2_P(J31), CLKout2_N(J34), CLKout3_P(J20), CLKout3_N(J17), CLKout4_P(J32), CLKout4_N(J35), CLKout5_P(J21), CLKout5_N(J18), CLKout6_P(J33), CLKout6_N(J36), CLKout7_P(J22), CLKout7_N(J19), CLKout8_P(J37), CLKout8_N(J40), CLKout9_P(J26), CLKout9_N(J23),CLKout10_P(J38), CLKout10_N(J41), CLKout11_P(J27), CLKout11_N(J24), CLKout12_P(J39), CLKout12_N(J42), CLKout13_P(J28), CLKout13_N(J25) |
Analog,
Output |
Clock outputs with programmable output buffers.
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| The output terminations by default on the evaluation board are shown here: | ||||
| Clock Output Pair | Default Board Termination | |||
| CLKout0 | LVPECL / LCPECL, 240 Ω | |||
| CLKout1 | LVPECL / LCPECL, 240 Ω | |||
| CLKout2 | LVPECL / LCPECL, 120 Ω | |||
| CLKout3 | LVPECL / LCPECL, 120 Ω | |||
| CLKout4 | CML, 68 nH - 20 Ω | |||
| CLKout5 | CML, 50 Ω | |||
| CLKout6 | CML, 68 nH - 20 Ω | |||
| CLKout7 | CML, 50 Ω | |||
| CLKout8 | CML, 50 Ω | |||
| CLKout9 | LVDS / HSDS | |||
| CLKout10 | CML, 13 nH - 20 Ω | |||
| CLKout11 | LVDS / HSDS | |||
| CLKout12 | LVPECL / LCPECL, 180 Ω | |||
| CLKout13 | LVPECL / LCPECL, 180 Ω | |||
| Each CLKout pair has a programmable LVDS, LVPECL, LCPECL, HSDS, CML, or LVCMOS buffer. The output buffer type can be selected in TICS Pro in the Clock Outputs page Section A.9 through the CLKoutX_FMT control.
All clock outputs are AC-coupled to allow safe testing with RF test equipment. If an output pair is programmed to LVCMOS, each output can be independently configured (normal, inverted, or off/tri-state). Best performance/EMI reduction is achieved by using a complementary output mode like Norm/Inv. It is not recommended to use Norm/Norm or Inv/Inv mode. |
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| OSCout
OSCout_P(J11) OSCout_N(J12) |
Analog,
Output |
Buffered outputs of OSCin port.
|
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| The output terminations on the evaluation board are shown here.: | ||||
| OSC Output Pair | Default Board Termination | |||
| OSCout | LVPECL, 240 Ω | |||
| OSCout has a programmable LVDS, LVPECL, or LVCMOS output buffer. The OSCout buffer type can be selected in TICS Pro on the Clock Outputs page Section A.9 through the OSCout_FMT control.
Note that OSCout is DC-coupled by default. In case RF test equipment cannot handle the OSCout voltage, please AC-couple OSCout by replacing C59 and C60 with capacitors. If OSCout is programmed as LVCMOS, each output can be independently configured (normal, inverted, inverted, and off/tri-state). Best performance/EMI reduction is achieved by using a complementary output mode like Norm/Inv. It is NOT recommended to use Norm/Norm or Inv/Inv mode. |
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| Power
VccEXT(J1/J2/TP3) Vcc(TP1) |
Power,
Input |
Main power supply input for the evaluation board.
The LMK04832EVM-CVAL default is setup to use the TPS7A4501HKU/EM voltage regulator. This is a space grade voltage regulator. 0-ohm resistors R3, R5, R6, R14 and R15 can be re-configured to route power through the on-board commercial grade LDO, the TPS7A4533KTTR. The LMK04832-SP contains internal voltage regulators for the VCO and other internal blocks. The clock outputs do not have an internal regulator, so a clean power supply with sufficient output current capability is required for optimal performance. If using an external voltage please ensure the voltage is filtered to get the best performance on the outputs. Apply power to either Vcc SMA(J1) or terminal block(J2), but not both. |
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| Clock Inputs
CLKin0_P(J5), CLKin0_N(J6), CLKin1_P(J8), CLKin1_N(J10) OSCout_P(J11), OSCout_N(J12) Fin0_P(J3),Fin0_N(J4) |
Analog,
Input |
Reference Clock Inputs for PLL1 or PLL1 (CLKin0, CLKin1, CLKin2)
CLKin1_N is configured by default for a single-ended reference clock input from a 50-ohm source. The non-driven input pin CLKin1_P is connected to GND with a 0.1 uF. CLKin0 is configured by default for a differential reference clock input from a 50-ohm source. CLKin1 is the default reference clock input selected in TICS Pro. If OSCout is to be used as a CLKin2, then the PCB must be updated to operate as an input instead of an output. |
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| Clock Distribution with Fin0 or CLKin1/Fin1
Fin0 and CLKin1 (Fin1) are shared for use as an RF Input for Clock Distribution mode or for an external VCO mode. |
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| External Feedback Input (FBCLKin) for 0-Delay
CLKin1 is shared for use as an external feedback clock input (FBCLKin) to PLL1 N or PLL2 N for 0-delay mode. Refer to the LMK04832-SP (SNAS698) data sheet for more details on using 0-delay mode with the evaluation board and the evaluation board software. |
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| OSCin, PLL2 reference/PLL1 feedback
OSCin_P(J13), OSCin_N(J14) |
Analog,
Input |
Feedback VCXO clock input to PLL1 and Reference clock input to PLL2.
The single-ended output of the onboard VCXO (Y1/Y2) drives the OSCin_N input of the device and the OSCin_P input of the device is connected to GND with 0.1 uF. VCXO Y1 and Y2 may also be used with differential VCXOs. An external VCXO may be optionally attached through these SMA connectors with minor modification to the components going to the OSCin pins of device. A single-ended or differential signal may be used to drive the OSCin pins and must be AC coupled. If operated in single-ended mode, the unused input must be connected to GND with 0.1 uF. Refer to the LMK04832-SP (SNAS698) data sheet section “Electrical Characteristics” for PLL2 Reference Input (OSCin) specifications (SNAS698). |
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| VCO Tuning Voltages
VTUNE1 (TP7/J7) VTUNE (TP8/J9) |
Analog,
Input/Output |
Tuning voltage output from the loop filter for PLL1 and PLL2 of the LMK04832-SP.
If an external VCXO is used, this tuning voltage can be connected to the voltage control pin of the external VCXO. The default board does not come with J7 and J9 populated. |
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| SPI Header
USB2ANY (J43) SDIO (TP17),SCK (TP14),CS* (TP19) CLKin_SEL0(TP10),CLKin_SEL1(TP11) RESET(TP13) |
CMOS,
Input/Output |
10-pin header for SPI programming interface and programmable logic I/O pins for the LMK04832-SP.
SPI signals include SDIO (TP17), SCK (TP14) and CS* (TP19). The programmable logic I/O signals accessible through this header include: RESET (TP13), SYNC (TP20/J44), CLKin_SEL0 (TP10), and CLKin_SEL1 (TP11). |
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| Input Clock Switching – Pin Select Mode
By default CLKin_SEL0 and CLKin_SEL1 are input pins. To enable input clock switching, CLKin_SEL_AUTO_EN = 0, CLKin_SEL_PIN_EN = 1, CLKin_SEL_PIN_POL = 0, and Status_CLKinX_TYPE must be 0 to 3 (pin enabled as an input). When CLKin_SEL_AUTO_EN = 0 and CLKin_SEL_PIN_EN = 1, the Status_CLKinX pins select which clock input is active as follows: |
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| CLKin_SEL1 | CLKin_SEL0 | Active Clock | ||
| 0 | 0 | CLKin0 | ||
| 0 | 1 | CLKin1 | ||
| 1 | 0 | CLKin2 | ||
| 1 | 1 | Holdover | ||
| SYNC
SYNC (TP20/J44) |
CMOS,
Input/Output |
Programmable status I/O pin. By default, set as an input pin for synchronize the clock outputs with a fixed and known phase relationship between each clock output selected for SYNC. A SYNC event also causes the digital delay values to take effect.
SYNC/SYSREF_REQ pin forces the SYSREF_MUX into SYSREF Continuous mode (0x03) when SYSREF_REQ_EN = 1. SYNC/SYSREF_REQ pin can hold outputs in a low state, depending on system configuration. SYNC_POL adjusts for active low or active high control. A SYNC event can also be programmed by toggling the SYNC_POL_INV bit in the SYNC/SYSREF page Section A.8 in TICS Pro. |
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| Status LEDs
Status_LD1(TP18),Status_LD2(TP21) |
CMOS,
Input/Output |
Programmable status output pin. By default, Status_LD1 and Status_LD2 are set to output the digital lock detect status signal for PLL1 and the digital lock detect status signal for PLL2 respectively.
By default TICS Pro configuration, LEDs will illuminate green when lock is detected (output is high) and turned off when lock is lost (output is low). |
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