米6体育平台手机版

SNAU252 June 2020 LMK04832-SP

LMK04832EVM-CVAL User’s Guide
A TICS Pro Usage
1. A.1 Communication Setup
2. A.2 User Controls
3. A.3 Raw Registers Page
4. A.4 Set Modes Page
5. A.5 Holdover Page
6. A.6 CLKinX Control Page
7. A.7 PLL1 and 2 Page
8. A.8 SYNC / SYSREF Page
9. A.9 Clock Outputs Page
10. A.10 Other Page
11. A.11 Current Calculator Page
12. A.12 Burst Page

A.7 PLL1 and 2 Page

The PLL1 and PLL2 page shows the frequencies that the PLL1 and PLL2 operate at. In distribution mode, the CLKin1 frequency will directly be connected to the VCO/clock distribution path frequency. In addition to the basic PLL dividers and controls, when the PLLX_NCLK_MUX selects the feedback mux as a source, 0-delay modes are achieved. When enabling 0-delay red text will help guide the user through properly setting up 0-delay mode.

When using dual PLL mode, the OSCin Source combo box can be set to External VCXO which links the OSCin frequency with the external VCXO frequency. When using single PLL2 mode, the OSCin Source combo box can be set to Independent to allow the OSCin frequency to be unlinked from the external VCXO frequency.

Figure 19. TICS Pro - PLL1 and 2 Page