The LMK04368-EP offers programmable clock output buffer formats, the evaluation board is shipped with pre-configured output terminations. Refer to Table 6-1 to see the list of output formats available and what output formats your hardware is configured for out of the factory.

To measure phase noise at one of the clock outputs (for example, CLKout0):

1. Go to the Clock Outputs page (Section 11.9).
2. Uncheck CLKoutX_Y_PD in the Clock Output box to enable the channel.
3. Set the following as needed:
   1. For Device Clock:
      1. DCLKX_Y_PD = 0 in Clock Mode Select box
      2. Set Bypass Div (DCLKX_Y_BYP) or Clock Divider (DCLK0_1_DIV) as desired for device clock frequency:
         1. If bypass mode is set, CLKoutX must be set to a CML output format. Bypass mode is not available on CLKoutY.
         2. If Clock Divider = 1, then DCLKX_Y_DCC must be set for clock output.
      3. Phase of the device clock can be adjusted with:
         1. Static Digital delay (DCLKX_Y_DDLY) after a SYNC. Digital Delay (DCLKX_Y_DDLY_PD) must be powered up.
         2. Dynamic Digital delay (DDLYdX_EN), then programming DDLYd_STEP_CNT. Digital Delay (DCLKX_Y_DDLY_PD) must be powered up. Press the Send button at top-right of Clock Outputs window to program the DDLYd_STEP_CNT field multiple times.
         3. Half Step bit (DCLKX_Y_HS) if DCC & HS (DCLKX_Y_DCC) is set.
         4. The Polarity bit (DCLKX_Y_POL)
      4. Select the device clock for CLKoutX or CLKoutY with CLKout#_SRC_MUX = 0 (Device Clock) as desired.
   2. While the phase noise of a SYSREF Clock is typically not of concern, to configure an output for SYSREF:
      1. SCLKX_Y_PD = 0 in Clock Mode Select box
      2. Phase of the SYSREF clock can be adjusted:
         1. Local digital delay can be set with SCLKX_Y_DDLY.
         2. Local analog delay can be set by enabling with ADLY_EN = 1 (SCLKX_Y_ADLY_EN) and then setting SCLKX_Y_ADLY to the desired time delay.
         3. Global digital delay can be set with SYSREF_DDLY, but this delay change will take effect only after a SYNC.
      3. Enable SYSREF outputs globally. The necessary bits depend upon the type of SYSREF to be enabled. For a simple continuous SYSREF (not recommended in final application due to extra power consumption and crosstalk), set SYSREF_PD = 0, SYSREF_MUX = 0x03 (Continuous), and SYNC_DISSYSREF = 1.
      4. Select the SYSREF clock for CLKoutX or CLKoutY with CLKout#_SRC_MUX = 1 (SYSREF) as desired.
   Figure 5-4 Setting Digital Delay, Clock Divider, Analog Delay, and Output Format.
4. Depending on the configured output type, the clock output SMAs can be interfaced to a test instrument with a single-ended, 50-Ω input as follows:
   1. For LVDS:
      1. A balun (like ADT2-1T or a high-quality Prodyn BIB-100G) is recommended for differential-to-single-ended conversion.
   2. For LVPECL:
      1. A balun can be used, or
      2. One side of the LVPECL signal can be terminated with a 50-Ω load and the other side can be run single-ended to the instrument.
   3. For HSDS:
      1. A balun (like ADT2-1T or high-quality Prodyn BIB-100G) is recommended for differential-to-single-ended conversion.
   4. For CML:
      1. A balun can be used, or
      2. One side of the CML signal can be terminated with a 50-Ω load and the other side can be run single-ended to the instrument.
   5. For LVCMOS:
      1. Connect the LVCMOS signal to measurement equipment as desired. If an output of a pair is not used, TI recommends leaving the output floating close to the IC. Alternatively, place a 50-Ω termination at the end of an unused trace.
5. The phase noise may be measured with a spectrum analyzer or signal source analyzer.