3 PLL Loop Filters and Loop Parameters

In jitter cleaning applications that use a cascaded or dual PLL architecture, the first PLL’s purpose is to substitute the phase noise of a low-noise oscillator (VCXO) for the phase noise of a dirty reference clock. The first PLL is typically configured with a narrow loop bandwidth to minimize the impact of the reference clock phase noise. The reference clock consequently serves only as a frequency reference rather than a phase reference.

The loop filters on the LMK04368EPEVM evaluation board are set up using the approach above. The loop filter for PLL1 has been configured for a narrow loop bandwidth (< 1 kHz). The specific loop bandwidth values depend on the phase noise performance of the oscillator mounted on the board. Table 3-1 and Table 3-2 contain the parameters for PLL1 and PLL2 for each oscillator option.

TI’s PLLatinum™ Simulation tool can be used to optimize PLL phase noise/jitter for given specifications. See http://www.ti.com/tool/pllatinumsim-sw for more information.