SNAU295 July 2024 LMK5C33216A
- 1
- Abstract
- Trademarks
- 1Introduction
- 2EVM Quick Start
- 3EVM Configuration
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4EVM Schematics
- 4.1 Power Supply Schematic
- 4.2 Alternative Power Supply Schematic
- 4.3 Power Distribution Schematic
- 4.4 LMK5C33216A and Input References IN0 to IN1 Schematic
- 4.5 Clock Outputs OUT0 to OUT3 Schematic
- 4.6 Clock Outputs OUT4 to OUT9 Schematic
- 4.7 Clock Outputs OUT10 to OUT15 Schematic
- 4.8 XO Schematic
- 4.9 Logic I/O Interfaces Schematic
- 4.10 USB2ANY Schematic
- 5EVM Bill of Materials
- 6Appendix A - TICS Pro LMK5B33216 Software
6.1.3 Step 3
Set the clock input select mode for the DPLLs, input priority, and maximum TDC frequency. The recommended Input Select Mode is Auto Revertive. REF0 and REF1 shown below correspond with IN0 and IN1, respectively. REF4 and REF5 priorities can be set if the DPLLs input is fed from one of the APLL post divider frequencies. The corresponding APLL is listed next to the REF4 and REF5. The REF with the highest priority is fed as the DPLL input.
Figure 6-3 Step 3: DPLL Clock Input Selection