The LMK5C33216A has an XO input (XO pin) to accept a reference clock for the Fractional-N APLLs. The XO input determines the output frequency accuracy and stability in free-run or holdover modes. For synchronization applications like SyncE or IEEE 1588, the XO input is typically driven by a low-frequency TCXO or OCXO that conforms to the frequency accuracy and holdover stability requirements of the application. For proper DPLL operation, the XO frequency must have a non-integer frequency relationship with the VCO output frequency of any APLLs that uses the XO input as the reference. The non-integer relationship must be greater than 0.05 away from an integer boundary (meaning > 0.05 and < 0.95). When configuring the LMK5C33216A as a clock generator (DPLL not used), then the XO frequency can have an integer relationship with the APLL output frequency.

The XO input of the LMK5C33216A has programmable on-chip input termination and AC-coupled input biasing options to support any clock interface type.

Figure 3-9 XO Input