SNAU295 July   2024 LMK5C33216A

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2EVM Quick Start
  6. 3EVM Configuration
    1. 3.1  Power Supply
    2. 3.2  Logic Inputs and Outputs
    3. 3.3  Switching Between I2C and SPI
    4. 3.4  Generating SYSREF Request
    5. 3.5  XO Input
      1. 3.5.1 48MHz TCXO (Default)
      2. 3.5.2 External Clock Input
      3. 3.5.3 Additional XO Input Options
      4. 3.5.4 APLL Reference Options
    6. 3.6  Reference Clock Inputs
    7. 3.7  Clock Outputs
    8. 3.8  Status Outputs and LEDS
    9. 3.9  Requirements for Making Measurements
    10. 3.10 Typical Phase Noise Characteristics
  7. 4EVM Schematics
    1. 4.1  Power Supply Schematic
    2. 4.2  Alternative Power Supply Schematic
    3. 4.3  Power Distribution Schematic
    4. 4.4  LMK5C33216A and Input References IN0 to IN1 Schematic
    5. 4.5  Clock Outputs OUT0 to OUT3 Schematic
    6. 4.6  Clock Outputs OUT4 to OUT9 Schematic
    7. 4.7  Clock Outputs OUT10 to OUT15 Schematic
    8. 4.8  XO Schematic
    9. 4.9  Logic I/O Interfaces Schematic
    10. 4.10 USB2ANY Schematic
  8. 5EVM Bill of Materials
    1. 5.1 Loop Filter and Vibration Nonsensitive Capacitors
  9. 6Appendix A - TICS Pro LMK5B33216 Software
    1. 6.1  Using the Start Page
      1. 6.1.1 Step 1
      2. 6.1.2 Step 2
      3. 6.1.3 Step 3
      4. 6.1.4 Step 4
      5. 6.1.5 Step 5
      6. 6.1.6 Step 6
      7. 6.1.7 Step 7
    2. 6.2  Using the Status Page
    3. 6.3  Using the Input Page
      1. 6.3.1 Cascaded Configurations
        1. 6.3.1.1 Cascade VCO to APLL Reference
    4. 6.4  Using APLL1, APLL2, and APLL3 Pages
      1. 6.4.1 APLL DCO
    5. 6.5  Using the DPLL1, DPLL2, and DPLL3 Pages
      1. 6.5.1 DPLL DCO
    6. 6.6  Using the Validation Page
    7. 6.7  Using the GPIO Page
      1. 6.7.1 SYNC/SYSREF/1-PPS Page
    8. 6.8  Using the Outputs Page
    9. 6.9  EEPROM Page
    10. 6.10 Design Report Page

3 EVM Configuration

The LMK5C33216A is a highly-configurable clock chip with multiple power domains, PLL domains, and clock input and output domains. To support a wide range of LMK5C33216A use cases, the EVM was designed with more flexibility and functionality than needed to implement the chip in a customer system application.

This section describes the power, logic, and clock input and output interfaces on the EVM, as well as how to connect, set up, and operate the EVM. Refer to Figure 4-1.

Table 3-1 Key Components Reference Designators and Descriptions
ITEM NO. REFERENCE

DESIGNATORS

 DESCRIPTION
1 U1 LMK5C33216A
2 J500 (VIN4 terminal block header) External Supply, +12-V DC using default configuration.
3 A Y1

Onboard TCXO. Y1 provides improved holdover stability and allow narrower DPLL loop bandwidths to be used in comparison to the external XO input.

B

J8

SMA connector for external XO. To use the external XO, remove the jumper from JP4.
4 J4/5, J6/7 SMA Ports for Clock Inputs (IN0_P/N and IN1_P/N).

IN0_N is not populated and IN0_P is configured for single ended input. IN1 is configured for differential input.
5 J9/11, J10/12, J13/15, J14/16, J17/19, J18/20, J21/J23, J22/24, J25/27, J26/28, J29/31, J30/32, J33/35, J34/36, J37/39, J38/40 SMA Ports for Clock Outputs
6 S5 Normally open. Push button for device power down (PDN pin). R76 enables control of the PDN pin through the GUI.

R76 is installed by default.
7 JP5

Jumper header for I2C/SPI interface (MCU to LMK5C33216A)
8 D6 SCL or SCK busy indication LED.
9 J41 USB Port for MCU
LMK5C33216AEVM Key Components - EVM Top Side Figure 3-1 Key Components - EVM Top Side
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