The logic input and output pins on LMKDB1102 and
LMKDB1202 provides option for output active / inactive control, loss of signal (LOS)
detection, and output impedance selection. LMKDB1202 offers an additional input clock
selection pin, CLKIN_SEL_tri.
Table 3-2 Clock Input Selection (only for
LMKDB1202)| CLKIN_SEL_tri Input Level | Function |
|---|
| Low (default) | CLKIN0 is the input source for all outputs. |
| High | CLKIN1 is the input source for all outputs. |
| Hi-Z | CLKIN0 is the input source for OUT1 outputs and CLKIN1 is the
input source for OUT2 outputs. |
Table 3-3 Output Enable Pin Control| OE1# and OE2# Input Level | OUTPUT STATUS |
|---|
| Low (default) | Active |
| High | Inactive |
Table 3-4 Loss of Signal (LOS) Detection (Status pin)| LOSb OUTPUT LEVEL | LOS STATUS |
|---|
| Low | Not detected |
| High | Detected |
Table 3-5 LP-HCSL Differential CLock Output Impedance Select| ZOUT_SEL Input Level | Function |
|---|
| Low (default) | LMKDB1x02 has 85Ω output termination |
| High | LMKDB1x02 has 100Ω output termination |