SNIU028D February   2016  – September 2020 UCD3138 , UCD3138064 , UCD3138064A , UCD3138128 , UCD3138A , UCD3138A64

 

  1. 1 Introduction
    1. 1.1 Scope of This Document
    2. 1.2 A Guide to Other Documentation for all Members of UCD3138 Family of Products
    3.     Trademarks
  2. 2 Digital Pulse Width Modulator (DPWM)
    1. 2.1  DPWM Block Diagram
    2. 2.2  Introduction to DPWM (DPWM Multi-Mode, Open Loop)
    3. 2.3  DPWM Normal Mode
    4. 2.4  DPWM Phase Shift Mode
    5. 2.5  DPWM Multiple Output Mode (Multi Mode)
    6. 2.6  DPWM Resonant Mode
    7. 2.7  Triangular Mode
    8. 2.8  DPWM Leading Edge Mode
    9. 2.9  Sync FET Ramp and IDE Calculation
    10. 2.10 Automatic Mode Switching
      1. 2.10.1 Resonant LLC Example
      2. 2.10.2 Mechanism for Automatic Mode Switching
    11. 2.11 DPWMC, Edge Generation, IntraMax
    12. 2.12 Time Resolution of Various DPWM Registers
    13. 2.13 PWM Counter and Clocks
    14. 2.14 DPWM Registers - Overview
    15. 2.15 DPWM Control Register 0 (DPWMCTRL0)
      1. 2.15.1  DPWM Auto Config Mid and Max Registers
      2. 2.15.2  Intra Mux
      3. 2.15.3  Cycle by Cycle Current Limit Enable
      4. 2.15.4  Multi Mode On/Off
      5. 2.15.5  Minimum Duty Mode
      6. 2.15.6  Master Sync Control Select
      7. 2.15.7  Master Sync Slave Enable
      8. 2.15.8  D Enable
      9. 2.15.9  Resonant Mode Fixed Duty Enable
      10. 2.15.10 DPWM A and B Fault Priority
      11. 2.15.11 Blank Enable
      12. 2.15.12 DPWM Mode
      13. 2.15.13 DPWM Invert
      14. 2.15.14 1.15.14 Filter Enable (CLA_EN)
      15. 2.15.15 DPWM Enable
    16. 2.16 DPWM Control Register 1
      1. 2.16.1  Period Counter Preset Enable
      2. 2.16.2  Sync FET Ramp Enable
      3. 2.16.3  Burst Mode Enable
      4. 2.16.4  Current/Flux Balancing Duty Adjust
      5. 2.16.5  1.16.5 Sync Out Divisor Selection
      6. 2.16.6  FIlter Scale
      7. 2.16.7  External Sync Enable
      8. 2.16.8  Cycle By Cycle B Side Active Enable
      9. 2.16.9  Auto Mode Switching Enable
      10. 2.16.10 1.16.10 Event Update Select
      11. 2.16.11 Check Override
      12. 2.16.12 Global Period Enable
      13. 2.16.13 Using DPWM Pins as General Purpose I/O
      14. 2.16.14 High Resolution enable/disable
      15. 2.16.15 Asynchronous Protection Disable
      16. 2.16.16 Single Frame Enable
    17. 2.17 DPWM Control Register 2
      1. 2.17.1 External Synchronization Input Divide Ratio
      2. 2.17.2 Resonant Deadtime Compensation Enable
      3. 2.17.3 Filter Duty Select
      4. 2.17.4 IDeal Diode Emulation (IDE) Enable for PWMB
      5. 2.17.5 Sample Trigger 1 Oversampling
      6. 2.17.6 Sample Trigger 1 Mode
      7. 2.17.7 Sample Trigger Enable Bits
    18. 2.18 Period and Event Registers
    19. 2.19 Phase Trigger Registers
    20. 2.20 Cycle Adjust Registers
    21. 2.21 Resonant Duty Register
    22. 2.22 DPWM Fault Control Register
    23. 2.23 DPWM Overflow Register
    24. 2.24 DPWM Interrupt Register
      1. 2.24.1 DPWM Period Interrupt Bits
      2. 2.24.2 Mode Switching Interrupt Bits
      3. 2.24.3 INT Bit
    25. 2.25 DPWM Counter Preset Register
    26. 2.26 Blanking Registers
    27. 2.27 DPWM Adaptive Sample Register
    28. 2.28 DPWM Fault Status Register
    29. 2.29 DPWM Auto Switch Registers
    30. 2.30 DPWM Edge PWM Generation Register
    31. 2.31 DPWM 0-3 Registers Reference
      1. 2.31.1  DPWM Control Register 0 (DPWMCTRL0)
      2. 2.31.2  DPWM Control Register 1 (DPWMCTRL1)
      3. 2.31.3  DPWM Control Register 2 (DPWMCTRL2)
      4. 2.31.4  DPWM Period Register (DPWMPRD)
      5. 2.31.5  DPWM Event 1 Register (DPWMEV1)
      6. 2.31.6  DPWM Event 2 Register (DPWMEV2)
      7. 2.31.7  DPWM Event 3 Register (DPWMEV3)
      8. 2.31.8  DPWM Event 4 Register (DPWMEV4)
      9. 2.31.9  DPWM Sample Trigger 1 Register (DPWMSAMPTRIG1)
      10. 2.31.10 DPWM Sample Trigger 2 Register (DPWMSAMPTRIG2)
      11. 2.31.11 DPWM Phase Trigger Register (DPWMPHASETRIG)
      12. 2.31.12 DPWM Cycle Adjust A Register (DPWMCYCADJA)
      13. 2.31.13 DPWM Cycle Adjust B Register (DPWMCYCADJB)
      14. 2.31.14 DPWM Resonant Duty Register (DPWMRESDUTY)
      15. 2.31.15 DPWM Fault Control Register (DPWMFLTCTRL)
      16. 2.31.16 DPWM Overflow Register (DPWMOVERFLOW)
      17. 2.31.17 DPWM Interrupt Register (DPWMINT)
      18. 2.31.18 DPWM Counter Preset Register (DPWMCNTPRE)
      19. 2.31.19 DPWM Blanking A Begin Register (DPWMBLKABEG)
      20. 2.31.20 DPWM Blanking A End Register (DPWMBLKAEND)
      21. 2.31.21 DPWM Blanking B Begin Register (DPWMBLKBBEG)
      22. 2.31.22 DPWM Blanking B End Register (DPWMBLKBEND)
      23. 2.31.23 DPWM Minimum Duty Cycle High Register (DPWMMINDUTYHI)
      24. 2.31.24 DPWM Minimum Duty Cycle Low Register (DPWMMINDUTYLO)
      25. 2.31.25 DPWM Adaptive Sample Register (DPWMADAPTIVE)
      26. 2.31.26 DPWM Fault Status (DPWMFLTSTAT)
      27. 2.31.27 DPWM Auto Switch High Upper Thresh Register (DPWMAUTOSWHIUPTHRESH)
      28. 2.31.28 DPWM Auto Switch High Lower Thresh Register (DPWMAUTOSWHILOWTHRESH)
      29. 2.31.29 DPWM Auto Switch Low Upper Thresh Register (DPWMAUTOSWLOUPTHRESH)
      30. 2.31.30 DPWM Auto Switch Low Lower Thresh Register (DPWMAUTOSWLOLOWTHRESH)
      31. 2.31.31 DPWM Auto Config Max Register (DPWMAUTOMAX)
      32. 2.31.32 DPWM Auto Config Mid Register (DPWMAUTOMID)
      33. 2.31.33 DPWM Edge PWM Generation Control Register (DPWMEDGEGEN)
      34. 2.31.34 DPWM Filter Duty Read Register (DPWMFILTERDUTYREAD)
      35. 2.31.35 DPWM BIST Status Register (DPWMBISTSTAT)
  3. 3 Front End
    1. 3.1 Error ADC and Front End Gain
      1. 3.1.1 Front End Gain
      2. 3.1.2 EADC Error Output
      3. 3.1.3 EADC Triggering, EADC Output to Filter
      4. 3.1.4 EADC Timing
      5. 3.1.5 EADC Averaging
      6. 3.1.6 Enabling EADC and Front End
    2. 3.2 Front End DAC
    3. 3.3 Ramp Module
      1. 3.3.1 DAC Ramp Overview
      2. 3.3.2 DAC Ramp Start and End Points
      3. 3.3.3 DAC Ramp Steps
      4. 3.3.4 DAC Ramp Start, Interrupts, Start Delay
      5. 3.3.5 RAMPSTAT Register
      6. 3.3.6 DAC RAMP when EADC is Saturated
      7. 3.3.7 Using Ramp Module for Peak Current Mode
      8. 3.3.8 Sync FET Soft On/Off using Ramp Module
    4. 3.4 Successive Approximation Mode
      1. 3.4.1 SAR Control Parameters
      2. 3.4.2 SAR Algorithm Overview
      3. 3.4.3 Non-Continuous SAR Mode
      4. 3.4.4 Continuous SAR Mode
    5. 3.5 Absolute Value Without SAR
    6. 3.6 EADC Modes
    7. 3.7 Front End Control Registers
      1. 3.7.1  Ramp Control Register (RAMPCTRL)
      2. 3.7.2  Ramp Status Register (RAMPSTAT)
      3. 3.7.3  Ramp Cycle Register (RAMPCYCLE)
      4. 3.7.4  EADC DAC Value Register (EADCDAC)
      5. 3.7.5  Ramp DAC Ending Value Register (RAMPDACEND)
      6. 3.7.6  DAC Step Register (DACSTEP)
      7. 3.7.7  DAC Saturation Step Register (DACSATSTEP)
      8. 3.7.8  EADC Trim Register (EADCTRIM) – (For Factory Test Use Only)
      9. 3.7.9  EADC Control Register (EADCCTRL)
      10. 3.7.10 Analog Control Register (ACTRL) (For Test Use Only)
      11. 3.7.11 Pre-Bias Control Register 0 (PREBIASCTRL0)
      12. 3.7.12 Pre-Bias Control Register 1 (PREBIASCTRL1)
      13. 3.7.13 SAR Control Register (SARCTRL)
      14. 3.7.14 SAR Timing Register (SARTIMING)
      15. 3.7.15 EADC Value Register (EADCVALUE)
      16. 3.7.16 EADC Raw Value Register (EADCRAWVALUE)
      17. 3.7.17 DAC Status Register (DACSTAT)
  4. 4 Filter
    1. 4.1  Filter Math Details
      1. 4.1.1 Filter Input and Branch Calculations
      2. 4.1.2 Proportional Branch
      3. 4.1.3 Integral Branch
      4. 4.1.4 Differential Branch
      5. 4.1.5 Add, Saturate, Scale and Clamp
      6. 4.1.6 Filter Output Stage
    2. 4.2  Filter Status Register
    3. 4.3  Filter Control Register
      1. 4.3.1  Filter Enable
      2. 4.3.2  Use CPU Sample
      3. 4.3.3  Force Start
      4. 4.3.4  Kp Off, Kd Off, Ki Off
      5. 4.3.5  Kd Stall, Ki Stall
      6. 4.3.6  Nonlinear Mode
      7. 4.3.7  Output Scaling
      8. 4.3.8  Output Multiplier Select
      9. 4.3.9  Switching Period as Output Multiplier
      10. 4.3.10 KComp as Output Multiplier
      11. 4.3.11 Feed Forward as Output Multiplier
      12. 4.3.12 Period Multiplier Select
      13. 4.3.13 Ki Adder Mode
    4. 4.4  XN, YN Read and Write Registers
      1. 4.4.1 CPU Xn Register
      2. 4.4.2 Filter XN Read Register
      3. 4.4.3 Filter YN Read Registers
    5. 4.5  Coefficient Configuration Register
    6. 4.6  Kp, Ki, and Kd Registers
    7. 4.7  Alpha Registers
    8. 4.8  Filter Nonlinear Limit Registers
    9. 4.9  Clamp Registers
    10. 4.10 Filter Preset Register
    11. 4.11 Filter Registers Reference
      1. 4.11.1  Filter Status Register (FILTERSTATUS)
      2. 4.11.2  Filter Control Register (FILTERCTRL)
      3. 4.11.3  CPU XN Register (CPUXN)
      4. 4.11.4  Filter XN Read Register (FILTERXNREAD)
      5. 4.11.5  Filter KI_YN Read Register (FILTERKIYNREAD)
      6. 4.11.6  Filter KD_YN Read Register (FILTERKDYNREAD)
      7. 4.11.7  Filter YN Read Register (FILTERYNREAD)
      8. 4.11.8  Coefficient Configuration Register (COEFCONFIG)
      9. 4.11.9  Filter KP Coefficient 0 Register (FILTERKPCOEF0)
      10. 4.11.10 Filter KP Coefficient 1 Register (FILTERKPCOEF1)
      11. 4.11.11 Filter KI Coefficient 0 Register (FILTERKICOEF0)
      12. 4.11.12 Filter KI Coefficient 1 Register (FILTERKICOEF1)
      13. 4.11.13 Filter KD Coefficient 0 Register (FILTERKDCOEF0)
      14. 4.11.14 Filter KD Coefficient 1 Register (FILTERKDCOEF1)
      15. 4.11.15 Filter KD Alpha Register (FILTERKDALPHA)
      16. 4.11.16 Filter Nonlinear Limit Register 0 (FILTERNL0)
      17. 4.11.17 Filter Nonlinear Limit Register 1 (FILTERNL1)
      18. 4.11.18 Filter Nonlinear Limit Register 2 (FILTERNL2)
      19. 4.11.19 Filter KI Feedback Clamp High Register (FILTERKICLPHI)
      20. 4.11.20 Filter KI Feedback Clamp Low Register (FILTERKICLPLO)
      21. 4.11.21 Filter YN Clamp High Register (FILTERYNCLPHI)
      22. 4.11.22 Filter YN Clamp Low Register (FILTERYNCLPLO)
      23. 4.11.23 Filter Output Clamp High Register (FILTEROCLPHI)
      24. 4.11.24 Filter Output Clamp Low Register (FILTEROCLPLO)
      25. 4.11.25 Filter Preset Register (FILTERPRESET)
  5. 5 Loop Mux
    1. 5.1  Front End Control Muxes (FECTRL0MUX, FECTRL1MUX, FECTRL2MUX)
    2. 5.2  Sample Trigger Control (SAMPTRIGCTRL)
    3. 5.3  External DAC Control (EXTDACCTRL)
    4. 5.4  Filter Mux Register (FILTERMUX)
    5. 5.5  Filter KComp Registers (FILTERKCOMPx)
    6. 5.6  DPWM Mux Register (DPWMMUX)
    7. 5.7  Global Enable Register (GLBEN)
    8. 5.8  PWM Global Period Register (PWMGLBPRD)
    9. 5.9  Sync Control (SYNCCTRL)
    10. 5.10 Light Load (Burst) Mode
    11. 5.11 Constant Current / Constant Power
    12. 5.12 Analog Peak Current Mode
    13. 5.13 Automatic Cycle Adjustment
      1. 5.13.1 Calculation
      2. 5.13.2 Configuration
      3. 5.13.3 Scaling
    14. 5.14 Loop Mux Registers Reference
      1. 5.14.1  Front End Control 0 Mux Register (FECTRL0MUX)
      2. 5.14.2  Front End Control 1 Mux Register (FECTRL1MUX)
      3. 5.14.3  Front End Control 2 Mux Register (FECTRL2MUX)
      4. 5.14.4  Sample Trigger Control Register (SAMPTRIGCTRL)
      5. 5.14.5  External DAC Control Register (EXTDACCTRL)
      6. 5.14.6  Filter Mux Register (FILTERMUX)
      7. 5.14.7  Filter KComp A Register (FILTERKCOMPA)
      8. 5.14.8  Filter KComp B Register (FILTERKCOMPB)
      9. 5.14.9  DPWM Mux Register (DPWMMUX)
      10. 5.14.10 Constant Power Control Register (CPCTRL)
      11. 5.14.11 Constant Power Nominal Threshold Register (CPNOM)
      12. 5.14.12 Constant Power Max Threshold Register (CPMAX)
      13. 5.14.13 Constant Power Configuration Register (CPCONFIG)
      14. 5.14.14 Constant Power Max Power Register (CPMAXPWR)
      15. 5.14.15 Constant Power Integrator Threshold Register (CPINTTHRESH)
      16. 5.14.16 Constant Power Firmware Divisor Register (CPFWDIVISOR)
      17. 5.14.17 Constant Power Status Register (CPSTAT)
      18. 5.14.18 Cycle Adjustment Control Register (CYCADJCTRL)
      19. 5.14.19 Cycle Adjustment Limit Register (CYCADJLIM)
      20. 5.14.20 Cycle Adjustment Status Register (CYCADJSTAT)
      21. 5.14.21 Global Enable Register (GLBEN)
      22. 5.14.22 PWM Global Period Register (PWMGLBPRD)
      23. 5.14.23 Sync Control Register (SYNCCTRL)
      24. 5.14.24 Light Load Control Register (LLCTRL)
      25. 5.14.25 Light Load Enable Threshold Register (LLENTHRESH)
      26. 5.14.26 Light Load Disable Threshold Register (LLDISTHRESH)
      27. 5.14.27 Peak Current Mode Control Register (PCMCTRL)
      28. 5.14.28 Analog Peak Current Mode Control Register (APCMCTRL)
      29. 5.14.29 Loop Mux Test Register (LOOPMUXTEST) (Test Use Only)
  6. 6 Fault Mux
    1. 6.1  Analog Comparator Configuration
      1. 6.1.1 ACOMP_EN
      2. 6.1.2 ACOMP_x_THRESH
      3. 6.1.3 ACOMP_x_POL
      4. 6.1.4 ACOMP_x_INT_EN
      5. 6.1.5 ACOMP_x_OUT_EN
      6. 6.1.6 ACOMP_x_SEL
      7. 6.1.7 ACOMP_F_REF_SEL
      8. 6.1.8 ACOMPCTRL Register Arrangement
    2. 6.2  Analog Comparator Ramp
    3. 6.3  Digital Comparator Configuration
    4. 6.4  Fault Pin Configuration
    5. 6.5  Analog Peak Current
    6. 6.6  Fault Status Registers
    7. 6.7  Fault Mux Control Registers
    8. 6.8  DPWM Fault Action
    9. 6.9  IDE / DCM Detection Control
    10. 6.10 Oscillator Failure Detection
      1. 6.10.1 High Frequency Oscillator Failure Detection
      2. 6.10.2 Low Frequency Oscillator Failure Detection
    11. 6.11 Fault Mux Registers Reference
      1. 6.11.1  Analog Comparator Control 0 Register (ACOMPCTRL0)
      2. 6.11.2  Analog Comparator Control 1 Register (ACOMPCTRL1)
      3. 6.11.3  Analog Comparator Control 2 Register (ACOMPCTRL2)
      4. 6.11.4  Analog Comparator Control 3 Register (ACOMPCTRL3)
      5. 6.11.5  External Fault Control Register (EXTFAULTCTRL)
      6. 6.11.6  Fault Mux Interrupt Status Register (FAULTMUXINTSTAT)
      7. 6.11.7  Fault Mux Raw Status Register (FAULTMUXRAWSTAT)
      8. 6.11.8  Comparator Ramp Control 0 Register (COMPRAMP0)
      9. 6.11.9  Digital Comparator Control 0 Register (DCOMPCTRL0)
      10. 6.11.10 Digital Comparator Control 1 Register (DCOMPCTRL1)
      11. 6.11.11 Digital Comparator Control 2 Register (DCOMPCTRL2)
      12. 6.11.12 Digital Comparator Control 3 Register (DCOMPCTRL3)
      13. 6.11.13 Digital Comparator Counter Status Register (DCOMPCNTSTAT)
      14. 6.11.14 DPWM 0 Current Limit Control Register (DPWM0CLIM)
      15. 6.11.15 DPWM 0 Fault AB Detection Register (DPWM0FLTABDET)
      16. 6.11.16 DPWM 0 Fault Detection Register (DPWM0FAULTDET)
      17. 6.11.17 DPWM 1 Current Limit Control Register (DPWM1CLIM)
      18. 6.11.18 DPWM 1 Fault AB Detection Register (DPWM1FLTABDET)
      19. 6.11.19 DPWM 1 Fault Detection Register (DPWM1FAULTDET)
      20. 6.11.20 DPWM 2 Current Limit Control Register (DPWM2CLIM)
      21. 6.11.21 DPWM 2 Fault AB Detection Register (DPWM2FLTABDET)
      22. 6.11.22 DPWM 2 Fault Detection Register (DPWM2FAULTDET)
      23. 6.11.23 DPWM 3 Current Limit Control Register (DPWM3CLIM)
      24. 6.11.24 DPWM 3 Fault AB Detection Register (DPWM3FLTABDET)
      25. 6.11.25 DPWM 3 Fault Detection Register (DPWM3FAULTDET)
      26. 6.11.26 HFO Fail Detect Register (HFOFAILDET)
      27. 6.11.27 LFO Fail Detect Register (LFOFAILDET)
      28. 6.11.28 IDE Control Register (IDECTRL)
  7. 7 GIO Module
    1. 7.1  Fault IO Direction Register (FAULTDIR)
    2. 7.2  Fault Input Register (FAULTIN)
    3. 7.3  Fault Output Register (FAULTOUT)
    4. 7.4  Fault Interrupt Enable Register (FAULTINTENA)
    5. 7.5  Fault Interrupt Polarity Register (FAULTINTPOL)
    6. 7.6  Fault Interrupt Pending Register (FAULTINTPEND)
    7. 7.7  External Interrupt Direction Register (EXTINTDIR)
    8. 7.8  External Interrupt Input Register (EXTINTIN)
    9. 7.9  External Interrupt Output Register (EXTINTOUT)
    10. 7.10 External Interrupt Enable Register (EXTINTENA)
    11. 7.11 External Interrupt Polarity Register (EXTTINTPOL)
    12. 7.12 External Interrupt Pending Register (EXTINTPEND)
    13. 7.13 References
  8. 8 ADC12 Overview
    1. 8.1  ADC12 Input Impedance Model
    2. 8.2  ADC12 Impedance vs. Sampling Frequency Data
    3. 8.3  Effect of External Capacitance
    4. 8.4  Channel to Channel Crosstalk
    5. 8.5  Impedance Roll-Off Due to Crosstalk
    6. 8.6  ADC12 Control FSM
    7. 8.7  Conversion
    8. 8.8  Sequencing
    9. 8.9  Digital Comparators
    10. 8.10 ADC Averaging
    11. 8.11 Temperature Sensor
    12. 8.12 Temp Sensor Control Register (TEMPSENCTRL)
    13. 8.13 PMBus Addressing
      1. 8.13.1 PMBus Control Register 3 (PMBCTRL3)
    14. 8.14 Dual Sample and Hold
      1. 8.14.1 ADC Control Register (ADCCTRL)
    15. 8.15 Usage of Sample and Hold Circuitry for High Impedance Measurement
      1. 8.15.1 C Code Example
    16. 8.16 ADC Configuration Examples
      1. 8.16.1 Software Initiated Conversions
      2. 8.16.2 Single Sweep Operation
      3. 8.16.3 Auto-Triggered Conversions
      4. 8.16.4 Continuous Conversions
      5. 8.16.5 Start/Stop Operation (External Trigger)
    17. 8.17 Useful C Language Statement Examples
    18. 8.18 ADC Registers
      1. 8.18.1  ADC Control Register (ADCCTRL)
      2. 8.18.2  ADC Status Register (ADCSTAT)
      3. 8.18.3  ADC Test Control Register (ADCTSTCTRL)
      4. 8.18.4  ADC Sequence Select Register 0 (ADCSEQSEL0)
      5. 8.18.5  ADC Sequence Select Register 1 (ADCSEQSEL1)
      6. 8.18.6  ADC Sequence Select Register 2 (ADCSEQSEL2)
      7. 8.18.7  ADC Sequence Select Register 3 (ADCSEQSEL3)
      8. 8.18.8  ADC Result Registers 0-15 (ADCRESULTx, x=0:15)
      9. 8.18.9  ADC Averaged Result Registers 0-5 (ADCAVGRESULTx, x=0:15)
      10. 8.18.10 ADC Digital Compare Limits Register 0-5 (ADCCOMPLIMx, x=0:5)
      11. 8.18.11 ADC Digital Compare Enable Register (ADCCOMPEN)
      12. 8.18.12 ADC Digital Compare Results Register (ADCCOMPRESULT)
      13. 8.18.13 ADC Averaging Control Register (ADCAVGCTRL)
  9. 9 Advanced Power Management Control Functions
    1. 9.1  Package ID Information
    2. 9.2  Brownout
    3. 9.3  Temperature Sensor Control
    4. 9.4  I/O Mux Control
    5. 9.5  Current Sharing Control
    6. 9.6  Temperature Reference
    7. 9.7  Power Disable Control or (Clock Gating Control)
    8. 9.8  Miscellaneous Analog Control Registers
      1. 9.8.1 Package ID Register (PKGID)
      2. 9.8.2 Brownout Register (BROWNOUT)
      3. 9.8.3 Temp Sensor Control Register (TEMPSENCTRL)
      4. 9.8.4 I/O Mux Control Register (IOMUX)
      5. 9.8.5 Current Sharing Control Register (CSCTRL)
      6. 9.8.6 Temperature Reference Register (TEMPREF)
      7. 9.8.7 Power Disable Control Register (PWRDISCTRL)
    9. 9.9  GPIO Overview
    10. 9.10 Interaction with a Single Pin
    11. 9.11 Interaction with Multiple Pins
    12. 9.12 Registers
      1. 9.12.1 Global I/O EN Register (GBIOEN)
      2. 9.12.2 Global I/O OE Register (GLBIOOE)
      3. 9.12.3 Global I/O Open Drain Control Register (GLBIOOD)
      4. 9.12.4 Global I/O Value Register (GLBIOVAL)
      5. 9.12.5 Global I/O Read Register (GLBIOREAD)
    13. 9.13 Need to Clear HFO_LN_FILTER_EN Bit
      1. 9.13.1 Clock Trim Register (CLKTRIM) (For Factory Test Use Only, Except HFO_LN_FILTER_EN)
  10. 10PMBus Interface/I2C Interface
    1. 10.1  PMBus Register Summary
    2. 10.2  PMBus Slave Mode Initialization
      1. 10.2.1 Initialization for Polling and Maximum Automatic Acknowledgement
      2. 10.2.2 Initialization for Interrupts and for Manual Acknowledgement
      3. 10.2.3 Initialization for I2C
      4. 10.2.4 Initialization for Advanced Features in Some Devices
        1. 10.2.4.1 Auto Acknowledge of Second Address
        2. 10.2.4.2 Clock High Timeout Detection
    3. 10.3  PMBus Slave Mode Command Examples
      1. 10.3.1  Write Command (Send Byte), No PEC
      2. 10.3.2  Other Simple Writes with Auto Acknowledge
      3. 10.3.3  Quick Command Write
      4. 10.3.4  Writes of 4 Bytes or More With Full Auto Acknowledge
      5. 10.3.5  Writes with Less than 3 Bytes Auto-Acknowledged
      6. 10.3.6  Manual Slave Address ACK for Write.
      7. 10.3.7  Manual Command ACK
      8. 10.3.8  Read Messages with Full Automation
      9. 10.3.9  Simple Read of 4 Bytes with Full Automation
      10. 10.3.10 Simple Read of More than 4 Bytes with Full Automation
      11. 10.3.11 Quick Command Read
      12. 10.3.12 Simple Read with Manual Slave Address ACK
      13. 10.3.13 Write/Read with Repeated Start
      14. 10.3.14 Automatic PEC Addition
    4. 10.4  Avoiding Clock Stretching
      1. 10.4.1 Using Early TXBUF Write to Avoid Clock Stretch
      2. 10.4.2 Alert Response
    5. 10.5  PMBus Slave Mode Low Level Timing
    6. 10.6  Effect of MAN_SLAVE_ACK bit on EOM Handling
    7. 10.7  Master Mode Operation Reference
      1. 10.7.1  Quick Command
      2. 10.7.2  Send Byte
      3. 10.7.3  Receive Byte
      4. 10.7.4  Write Byte/Word
      5. 10.7.5  Read Byte/Read Word
      6. 10.7.6  Process Call
      7. 10.7.7  Block Write
      8. 10.7.8  Block Read
      9. 10.7.9  Block Write-Block Read Process Call
      10. 10.7.10 Alert Response
      11. 10.7.11 Extended Command - Write Byte/Word, Read Byte/Word
      12. 10.7.12 Group Command
    8. 10.8  PMBUS Communications Fault Handling
      1. 10.8.1 Bit Counter
      2. 10.8.2 Test Mode (Manufacturer Reserved Address Match)
    9. 10.9  Other Functions of the PMBus Module
    10. 10.10 PMBus Interface Registers Reference
      1. 10.10.1 PMBUS Control Register 1 (PMBCTRL1)
      2. 10.10.2 PMBus Transmit Data Buffer (PMBTXBUF)
      3. 10.10.3 PMBus Receive Data Register (PMBRXBUF)
      4. 10.10.4 PMBus Acknowledge Register (PMBACK)
      5. 10.10.5 PMBus Status Register (PMBST)
      6. 10.10.6 PMBus Interrupt Mask Register (PMBINTM)
      7. 10.10.7 PMBus Control Register 2 (PMBCTRL2)
      8. 10.10.8 PMBus Hold Slave Address Register (PMBHSA)
      9. 10.10.9 PMBus Control Register 3 (PMBCTRL3)
  11. 11Timer Module Overview
    1. 11.1  T24 – 24 Bit Free-Running Timer with Capture and Compare
    2. 11.2  T24 Clock Source, Prescaler and Counter
    3. 11.3  T24 Capture Block
    4. 11.4  T24 Compare Blocks
    5. 11.5  T24 Interrupts
    6. 11.6  T16PWMx - 16 Bit PWM Timers
    7. 11.7  T16PWMx Summary
    8. 11.8  T16PWMx Prescaler and Counter
    9. 11.9  T16PWMx Compare Blocks
    10. 11.10 T16 Shadow Bit
    11. 11.11 T16 Interrupts
    12. 11.12 Using the T16 for a Timer Interrupt
    13. 11.13 Using the T16 for PWM Generation
    14. 11.14 WD - Watchdog
    15. 11.15 Watchdog Prescale and Counter
    16. 11.16 Watchdog Compare Blocks
    17. 11.17 Watchdog Protect Bit
    18. 11.18 Watchdog Timer Example
    19. 11.19 Warnings for Watchdog Status Register
    20. 11.20 System Fault Recovery Basics
    21. 11.21 Timer Module Register Reference
      1. 11.21.1  24-bit Counter Data Register (T24CNTDAT)
      2. 11.21.2  24-bit Counter Control Register (T24CNTCTRL)
      3. 11.21.3  24-bit Capture Channel Data Register (T24CAPDAT) or (T24CAPDATx)
      4. 11.21.4  24-bit Capture Channel Control Register (T24CAPCTRLx or T24CAPCTRL)
      5. 11.21.5  24-bit Capture I/O Control and Data Register (T24CAPIO)
      6. 11.21.6  24-bit Output Compare Channel 0 Data Register (T24CMPDAT0)
      7. 11.21.7  24-bit Output Compare Channel 1 Data Register (T24CMPDAT1)
      8. 11.21.8  24-bit Output Compare Channel 0 Control Register (T24CMPCTRL0)
      9. 11.21.9  24-bit Output Compare Channel 1 Control Register (T24CMPCTRL1)
      10. 11.21.10 PWMx Counter Data Register (T16PWMxCNTDAT)
      11. 11.21.11 PWMx Counter Control Register (T16PWMxCNTCTRL)
      12. 11.21.12 PWMx 16-bit Compare Channel 0-1 Data Register (T16PWMxCMPyDAT)
      13. 11.21.13 PWMx Compare Control Register (T16PWMxCMPCTRL)
      14. 11.21.14 Watchdog Status (WDST)
      15. 11.21.15 Watchdog Control (WDCTRL)
  12. 12UART Overview
    1. 12.1 UART Frame Format
    2. 12.2 Asynchronous Timing Mode
    3. 12.3 UART Interrupts
    4. 12.4 Transmit Interrupt
    5. 12.5 Receive Interrupt
    6. 12.6 Error Interrupts
    7. 12.7 UART Registers Reference
      1. 12.7.1  UART Control Register 0 (UARTCTRL0)
      2. 12.7.2  UART Receive Status Register (UARTRXST)
      3. 12.7.3  UART Transmit Status Register (UARTTXST)
      4. 12.7.4  UART Control Register 3 (UARTCTRL3)
      5. 12.7.5  UART Interrupt Status Register (UARTINTST)
      6. 12.7.6  UART Baud Divisor High Byte Register (UARTHBAUD)
      7. 12.7.7  UART Baud Divisor Middle Byte Register (UARTMBAUD)
      8. 12.7.8  UART Baud Divisor Low Byte Register (UARTLBAUD)
      9. 12.7.9  UART Receive Buffer (UARTRXBUF)
      10. 12.7.10 UART Transmit Buffer (UARTTXBUF)
      11. 12.7.11 UART I/O Control Register (UARTIOCTRLSCLK, UARTIOCTRLRX, UARTIOCTRLTX)
  13. 13Boot ROM and Boot Flash
    1. 13.1 Boot ROM Function
      1. 13.1.1 Initializing UCD3138
      2. 13.1.2 Verifying Checksums
      3. 13.1.3 Uses for 2 Different Checksums
      4. 13.1.4 Avoiding Program Flash Lockup
      5. 13.1.5 Using BOOT ROM PMBus Interface
    2. 13.2 Memory Read Functionality
      1. 13.2.1 Configure Read Address
      2. 13.2.2 Read 4 Bytes
      3. 13.2.3 Read 16 Bytes
      4. 13.2.4 Read Next 16 Bytes
    3. 13.3 Read Version
    4. 13.4 Memory Write Functionality
      1. 13.4.1 Write 4 Bytes
      2. 13.4.2 Write 16 Bytes
      3. 13.4.3 Write Next 16 Bytes
    5. 13.5 Flash Functions
      1. 13.5.1 Mass Erase
      2. 13.5.2 Page Erase
      3. 13.5.3 Execute Flash
      4. 13.5.4 Flash Programming Sequence using Boot ROM
    6. 13.6 Checksum Functions
      1. 13.6.1 Calculation of Checksum
      2. 13.6.2 Reading Checksum
    7. 13.7 Trim Flash Checksum Verification
    8. 13.8 Boot ROM for the Other Members of the UCD3138 Family
      1. 13.8.1 UCD3138064 and UCD3138064A
      2. 13.8.2 UCD3138A64 and UCD3138A64A
      3. 13.8.3 UCD3138128 and UCD3138128A
  14. 14ARM7TDMI-S MPUSS
    1. 14.1 ARM7TDMI-S Modes of Operation
      1. 14.1.1 Exceptions
    2. 14.2 Hardware Interrupts
      1. 14.2.1 Standard Interrupt (IRQ)
      2. 14.2.2 Fast Interrupt (FIQ)
    3. 14.3 Software Interrupt
    4. 14.4 ARM7TDMI-S Instruction Set
      1. 14.4.1 Instruction Compression
      2. 14.4.2 The Thumb Instruction Set
    5. 14.5 Dual-State Interworking
      1. 14.5.1 Level of Dual-State Support
      2. 14.5.2 Implementation
      3. 14.5.3 Naming Conventions for Entry Points (CCS 3.x)
      4. 14.5.4 Indirect Calls
      5. 14.5.5 UCD3138 Reference Code
  15. 15Memory
    1. 15.1 Memory Controller – MMC Registers Reference
      1. 15.1.1 Static Memory Control Register (SMCTRL)
      2. 15.1.2 Write Control Register (WCTRL)
      3. 15.1.3 Peripheral Control Register (PCTRL)
      4. 15.1.4 Peripheral Location Register (PLOC)
      5. 15.1.5 Peripheral Protection Register (PPROT)
    2. 15.2 DEC – Address Manager Registers Reference
      1. 15.2.1  Memory Fine Base Address High Register 0 (MFBAHR0)
      2. 15.2.2  Memory Fine Base Address Low Register 0 (MFBALR0)
      3. 15.2.3  1.1.1 Memory Fine Base Address High Register 1-3,17-19 (MFBAHRx)
      4. 15.2.4  Memory Fine Base Address Low Register 1-3, 17-19 (MFBALRx)
      5. 15.2.5  Memory Fine Base Address High Load Differences for Enhanced 3138 Devices
      6. 15.2.6  Memory Fine Base Address High Register 4 (MFBAHR4)
      7. 15.2.7  Memory Fine Base Address Low Register 4-16 (MFBALRx)
      8. 15.2.8  Memory Fine Base Address High Register 5 (MFBAHR5)
      9. 15.2.9  Memory Fine Base Address High Register 6 (MFBAHR6)
      10. 15.2.10 Memory Fine Base Address High Register 7 (MFBAHR7)
      11. 15.2.11 Memory Fine Base Address High Register 8 (MFBAHR8)
      12. 15.2.12 Memory Fine Base Address High Register 9 (MFBAHR9)
      13. 15.2.13 Memory Fine Base Address High Register 10 (MFBAHR10)
      14. 15.2.14 Memory Fine Base Address High Register 11 (MFBAHR11)
      15. 15.2.15 Memory Fine Base Address High Register 12 (MFBAHR12)
      16. 15.2.16 Memory Fine Base Address High Register 13 (MFBAHR13)
      17. 15.2.17 Memory Fine Base Address High Register 14 (MFBAHR14)
      18. 15.2.18 Memory Fine Base Address High Register 15 (MFBAHR15)
      19. 15.2.19 Memory Fine Base Address High Register 16 (MFBAHR16)
      20. 15.2.20 Program Flash Control Register (PFLASHCTRL)
      21. 15.2.21 Data Flash Control Register (DFLASHCTRL)
      22. 15.2.22 Flash Interlock Register (FLASHILOCK)
  16. 16Control System Module
    1. 16.1 Address Decoder (DEC)
      1. 16.1.1  Memory Mapping Basics
      2. 16.1.2  Why Change Memory Map?
      3. 16.1.3  How do Memory Map Registers Work?
      4. 16.1.4  RONLY Bit
      5. 16.1.5  Boot ROM Memory Initialization
      6. 16.1.6  Erasing the Programming Flash
      7. 16.1.7  Waiting for Flash Operations to Finish
      8. 16.1.8  Flash Interlock Register
      9. 16.1.9  Clearing RDONLY Bit
      10. 16.1.10 Switching from User Mode to Supervisor Mode
      11. 16.1.11 Erasing Data Flash
      12. 16.1.12 Writing to Data Flash
      13. 16.1.13 Erasing Program Flash
      14. 16.1.14 Writing to Program Flash
    2. 16.2 Memory Management Controller (MMC)
    3. 16.3 System Management (SYS)
    4. 16.4 Central Interrupt Module (CIM)
      1. 16.4.1 Interrupt Handling by CPU
      2. 16.4.2 Interrupt Generation at Peripheral
      3. 16.4.3 CIM Interrupt Management (CIM)
      4. 16.4.4 CIM Input Channel Management
      5. 16.4.5 CIM Prioritization
      6. 16.4.6 CIM Operation
      7. 16.4.7 Register Map
    5. 16.5 SYS – System Module Registers Reference
      1. 16.5.1 Clock Control Register (CLKCNTL)
      2. 16.5.2 System Exception Control Register (SYSECR)
      3. 16.5.3 System Exception Status Register (SYSESR)
      4. 16.5.4 Abort Exception Status Register (ABRTESR)
      5. 16.5.5 Global Status Register (GLBSTAT)
      6. 16.5.6 Device Identification Register (DEV)
      7. 16.5.7 System Software Interrupt Flag Register (SSIF)
      8. 16.5.8 System Software Interrupt Request Register (SSIR)
      9. 16.5.9 References
  17. 17Flash Memory Programming, Integrity, and Security
    1. 17.1 Quick Start Summary
      1. 17.1.1 ROM Bootstrap and Program Flash Checksum
      2. 17.1.2 Firmware Development Setup
      3. 17.1.3 Production Setup
    2. 17.2 Flash Memory Operations
      1. 17.2.1 UCD3138 Memory Maps
      2. 17.2.2 Flash Programming in ROM Mode
      3. 17.2.3 Clearing the Flash
      4. 17.2.4 3138 Family Members with Multiple Flash Blocks
    3. 17.3 Flash Management for Firmware Development
      1. 17.3.1 Best Practice for Firmware Development
      2. 17.3.2 Firmware Development with "Backdoors"
      3. 17.3.3 I/O Line Based Backdoors
        1. 17.3.3.1 Serial Port Based Backdoor
        2. 17.3.3.2 GPIO Line Based Backdoor
        3. 17.3.3.3 Other Options for I/O Backdoors
      4. 17.3.4 Communications Backdoors
        1. 17.3.4.1 Cautions for Using Communications Backdoors
    4. 17.4 Flash Management in Production
    5. 17.5 Firmware Examples
      1. 17.5.1 Checksum Clearing
      2. 17.5.2 Erasing Flash
      3. 17.5.3 Serial Port Based Backdoor
      4. 17.5.4 I/O Line Based Back Door
  18. 18CIM – Central Interrupt Module Registers Reference
    1. 18.1 IRQ Index Offset Vector Register (IRQIVEC)
    2. 18.2 FIQ Index Offset Vector Register (FIQIVEC)
    3. 18.3 FIQ/IRQ Program Control Register (FIRQPR)
    4. 18.4 Pending Interrupt Read Location Register (INTREQ)
    5. 18.5 Interrupt Mask Register (REQMASK)
  19. 19Revision History

12.6 Error Interrupts

The UCD3138’s UART module provides hardware indication of error conditions to provide information about the status of module operation. According to the data being assembled by the receiver, the UART monitors the data received for errors and sets the parity error (PE), framing error (FE), and/or the break-detect (BRKDT) flag when these conditions are detected.

In addition, the UART sets the overrun error (OE) flag if a transfer of new data from UARTRXSHF to UARTRXBUF overwrites unread data in UARTRXBUF. (If both overrun and parity errors occur, only the overrun error flag is set.)

The UART sets the wake-up flag (WAKEUP) if bus activity on the RX line either prevents power-down mode from being entered, or RX line activity causes an exit from power-down mode. Each of these flags is located in the receiver status (UARTRXST) register.

The RXERR flag, also in the UARTRXST register, is the logical OR of the parity error, framing error, overrun error, wake-up, and break-detect flags.

This UART Data Transfer feature allows software that is polling for receiver errors to check only one bit, which will indicate if any or all of the five error conditions are active.

Error interrupts are controlled by three separate enable bits: RXERR_INT_ENA, BRKDT_INT_ENA, and WAKEUP_INT_ENA.

If RXERR_INT_ENA (UARTCTRL3.0) is set, an error interrupt is generated when the receiver detects either a parity, framing, or overrun error. The break-detect interrupt is enabled separately.

If BRKDT_INT_ENA (UARTCTRL3.1) is set, an error interrupt is generated if the receiver detects a break condition. A break condition occurs when the SCI_RX line remains continuously low (active) for at least 10 bits immediately following a missed stop bit.

If WAKEUP_INT_ENA (UARTCTRL3.2) is set, an error interrupt is generated when bus activity on the RX line either prevents power-down mode from being entered or RX line activity causes an exit from power-down mode.
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