Using the Switching Period as an output multiplier leads to the DPWM duty being directly proportional to the Filter output, with a full range output being equal to about 100% of the period. Here is the bit pattern of the multiply:

The filter output is a 24 bit signed number, with a range from 0x7fffff (8388607) to 0x800000 (-8388608).

All of the output multipliers are unsigned 14 bit numbers with a range from 0x3fff (16383) to 0.

The product of these two numbers is a 38 bit number. This number is then scaled and rounded down to a 18 bit number and used for the high resolution events in the DPWM.

So suppose that the filter output is at about 50% or 4194304. If the period is the same as the example above, 2500, the product of the two will be 10485760000. To reduce this from a 38 bit signed number to a 18 bit unsigned number, we drop the sign bit off the top and divide by 2¹⁹. Negative filter outputs make no sense in terms of DPWM timing, so they will be clamped to zero.

Dividing by 2¹⁹ gives a result of 20000. This is a high resolution value for the 4 GHz clock of the DPWM. To convert it to the lower resolution, 250 MHz clock used for the period, we need to divide by 16. This gives a result of 1250, or half the period. Other filter output values follow the exact same scaling.

There is a register in the Loop Mux, the FILTERMUX register, which selects the period source for each filter.

See Section 5.15 for more information on this register. Here is an example of its use:

LoopMuxRegs.FILTERMUX.bit.FILTER0_PER_SEL = 2; //use DPWM2 period for filter 0