In UCD3138, there is another solution to this problem: use dual sample and hold circuitry. The dual sample and hold circuitry are designed to enable the sampling of two channels together, thus it’s suitable for power measurement, which requires that the sampling of voltage and current are in phase. There is only one conversion unit in UCD3138 ADC. But there are two S/H units to enable dual sample and hold function. The first one is the normal one we used for all channels. The second one shown in Figure 8-15 is the dual sample and hold S/H. If dual sample and hold function is enabled, two S/H units will work simultaneously. There is an S/H buffer inside the circuitry which makes the source impedance much lower. Thus this circuitry can be used for high impedance node measurement as well.

SEQx = y selects channel y to be converted in sequence x of the first S/H unit.

SEQx_SH = 1 enables the dual sample and hold S/H to sample at the same time as channel y.

BYPASS_EN selects the dual sample and hold channel. This register has 3 bits. 1 means bypass and 0 means connect to the S/H buffer. As shown in Figure 8-15.

Figure 8-15 Dual Sample and Hold Circuitry in ADC12

Figure 8-16 shows the ADC12 dual sample and hold configuration table and operation principles.

Figure 8-16 ADC12 Dual Sample and Hold Configuration

Here is an application example:

To use AD01 on high impedance node:

BYPASS_EN = 5; // select AD01 as dual sample and hold channel. A buffer will be added to AD01
SEQ0 = 4;      //put AD04 on sequence 0
SEQ0_SH = 1;   //enable AD04 to do dual sample and hold with AD01
SEQ1 = 1;      //put AD01 on sequence1