Two counters are used to detect a failure with the High Frequency Oscillator block. One counter is implemented in the High Frequency Oscillator clock domain, while the other counter is implemented in the Low Frequency Oscillator clock domain. The High Frequency Oscillator counter generates a clear signal once the counter reaches a firmware programmable 17-bit threshold. This clear signal clears the free running Low Frequency Oscillator counter. In the case of a High Frequency Oscillator failure, no clear signal is generated and the Low Frequency Oscillator counter will overflow, generating an oscillator fail flag to the SYS module. Based on the SYS module setup, a chip reset may be generated from the oscillator failure.

There are 2 bitfields in the HFO Failure detection register HFOFAILDET.

HFO_FAIL_THRESH – Configures threshold where a clear flag is used to clear a counter in the Low Frequency Oscillator domain (if LFO counter overflows, a reset will be generated), resolution of threshold equals High Frequency Oscillator perio

Bit 0: HFO_DETECT_EN – a 1 enables High Frequency Oscillator Failure Detection logic, device will be reset upon detection of an oscillator failure .

here is no interrupt or status bit for HFO failure. This is because if the HFO fails, the processor will not be working.