There is a register in the System Module – SYSESR – System Exception Status Register – which saves the reset cause through the reset. There is a bit for every event except the watchdog timer.

It is possible to look at this register when the program is entered and determine if the reset was caused by the watchdog timer, or some other cause, such as an illegal address access. Often if a problem occurs with firmware execution, some other fault will occur before the watchdog timer times out. So if a reset occurs and none of the bits are set, then the cause is the watchdog timer.

To use this register, examine it when the program is first started. Do whatever processing is necessary, save the reset cause if desired, and then clear the register. In this way, it will be possible to tell the next reset cause. If the register is not cleared by the program, there may be two bits set the next time, making it impossible to determine the cause of the newest reset.

All resets, regardless of the cause, will reset all of the peripherals to their default state, so most outputs will go to inputs and so on. This will generally have the effect of shutting down any power supply that is being controlled by the device.