The picture below illustrates an overall view of a single DPWM block, which is composed of many different individual modules, through which the signals propagate:

Figure 2-1 Block Diagram of a DPWM Module

• The Timing Generation Module outputs 3 DPWM signals (DPWMx_T, x=A, B, C), as well as many other signals for other modules. It is the section where the filter output is translated into pulse widths and sometimes into the period.
• The Fault Handling Module is next. It shuts off the DPWM signals if a fault occurs. After the DPWM signals come from the Fault Module (DPWMx_F, x=A, B, C), they are sent to other DPWM Modules.
• The Edge Generation and Intra Mux modules can combine signals from several DPWMs to generate new signals (DWMx_E, DPWMx_I, x=A, B, C).

The notation of DPWMx_T, DPWMx_F (where x=A, B, C) etc is very useful here to understand the origin and relationship between the signals. For example DPWM2A_F may have no relationship at all to DPWM2A_I.

Many topologies use neither the DPWMC signal nor Edge Generation and Intra Mux modules. The default is for these modules to just pass signals through unchanged. However certain topologies such as Phase Shifted Full Bridge (PSFB) use both modules as well as DPWMC signal.

These diagrams merely illustrate the signal propagation through the various modules in the DPWM and do not show the configuration logic which controls how each module works and which can dynamically reconfigure the DPWM between switching cycles.

Figure 2-2 shows a block diagram of just the Timing Module illustrating the data, signals and main elements involved (once again, the real logic of the Timing Module is not illustrated here).

Figure 2-2 Block Diagram of Timing Module in the DPWM module