The Digital Comparator is another fault detection mechanism. Instead of a direct analog input, it uses the result of the Front End EADC measurement to detect faults.

There are 4 Digital Comparators, controlled by the DCOMPCTRL0, 1, 2, and 3 registers.

They use the FE_SEL bitfield to select which Front End is used as a source, and whether the absolute or error data from that Front End is used.

Like the Analog Comparators, they can be programmed to detect a fault either above or below the threshold. The COMP_POL bit is used to select this.

There is also an INT_EN bit to enable the interrupt. Each Digital Comparator has its own COMP_EN bit to enable it.

The reference threshold for the comparator is much simpler, it only comes from the THRESH bit-field. It does have 11 bits of resolution, more than the Analog comparator.

The Digital Comparator adds a counter that can require several sequential fault detections before the signal is passed on to the Fault Mux.

The CNT_THRESH bitfield controls the number of fault detections required. Writing a 1 to the CNT_CLR bit will clear the counter and the associated fault.

If the counter reaches the CNT_THRESH value, it will be locked, and the DCOMP_x signal will be sent to the Fault Mux.

The Digital Comparator performs its comparison on each sample from the selected Front End. Fault detection can only occur after each sample from the Front End.

The CNT_CONFIG bit controls handling of sequences of samples which contain some fault samples and some non-fault samples. In the default mode – CNT_CONFIG = 0 – a non-fault sample will clear the counter (assuming it hasn’t reached CNT_THRESH).

If CNT_CONFIG = 1, a non-fault event will decrement the counter, unless the counter is already zero. With this setting, if the fault occurs more than 50% of the time, eventually the counter will reach the threshold.

There is also a DCOMPCNTSTAT register which gives the value in each of the counters. This register is read only.