The EADC is generally triggered by a sample trigger signal from a DPWM module. After this trigger, if averaging is enabled, additional triggers may come from the averaging module. The EADC can also be triggered by the Successive Approximation (SAR) module. Multiple DPWMS can be used to trigger a single EADC at different times in the same period.

Each DPWM module has 2 sample trigger registers to set sample trigger timing. The DPWMs can also provide oversampling of 2, 4, or 8 samples in coordination with 1 of the 2 sample triggers. See Section 2.18.5, for more information.

The Sample Trigger Control register in the Loop Mux module controls the routing of sample trigger signals from the DPWMs to the EADCs. There is a bit in that register for every possible DPWM/Front End combination. If that bit is set, then the sample trigger from that specific DPWM will be routed to that specific front end. For example, to use DPWM3 to trigger Front End 2, this is the code:

LoopMuxRegs.SAMPTRIGCTRL.bit.FE2_TRIG_DPWM3_EN = 1;

See Chapter 5 for more information.

If the EADC is driving a filter, that filter will compute its output at the conclusion of the EADC conversion. The Filter Mux register in the Loop Mux selects which front ends send data to which filters. For instance to send the output from Front End 2 to Filter 1:

LoopMuxRegs.FILTERMUX.bit.FILTER1_FE_SEL = 2; //use Front end 2 for filter 1.

See Chapter 5 for more information.

Sample triggers can also be divided so that the EADC only fires every 1 to 16 sample triggers:

FeCtrl0Regs.EADCCTRL.bit.SAMP_TRIG_SCALE = 4; //trigger every 5 sample triggers.