6.2 AC Capacitor on FPD3 Link

Figure 20. Simplified Block Diagram of DS90UB953-Q1/DS90UB954-Q1 System

The DS90UB953-Q1 FPD-Link III architecture is a 40-bit frame, high-speed synchronous back channel when communicating with 954 and 960. However, the mode that the device is operating in can change the data rate of the serial data output signal. For synchronous mode where the reference oscillator is provided by the deserializer, the serial data rate is 4 Gbps presented as a differential CML output on the DOUTP and DOUTN pins.

As shown in Figure 20, the signals at DOUTP and DOUTN must be AC-coupled with a series capacitor before the interconnect that leads to the deserializer. This AC-coupling capacitor will have a value of 0.033 μF when the device is running in 4-Gbps mode. At lower data rates, a larger coupling cap will be required. When connecting to a coax cable, the AC-coupling cap on the dummy side of the output (DOUTN) should also have an AC-coupling capacitor. This value should be half of the AC-coupling cap going to the cable (0.015 µF), and DOUTN should have a 50-Ω load on DOUTN. This load is needed because the AC and DC loads seen by DOUTP and DOUTN should be balanced. The capacitor on DOUTN should be half the value of the capacitor on DOUTP because the signal path must be balanced for the AC-coupling cap near the serializer and deserializer ends of the cable.

As mentioned previously, the AC capacitors will change if either the 953 or 954 are interfaced with lower data-rate parts such as 913A, 914A, 933, and 934. With a lower data-rate, the frequency band of interest is now lower in frequency and requires a larger capacitor.