2.1.1.2 Non-Synchronous CLK_IN Mode

Figure 5. Illustration of Non-Synchronous Mode With External Oscillator

The second mode, non-synchronous CLK_IN, uses an external oscillator as a reference and generates the required clock for the FPD forward channel for that reference. Referring to Figure 5, the external clock must be fed into the CLK_IN pin (20) on the 953, running at a constant rate (f1) proportional to the REFCLK (f0), and a BC rate is then programmed to be less than or equal to 10 Mbps. Register 0x05, GENERAL_CFG, on the 953 holds parameters for the PLL clock control. Bits [6:4] of this register control the CLKIN divider. The CLKIN Divider can be divided by 1 or 2 by assigning these bits to 0b000 or 0b001, respectively. This division must be accounted for when calculating the FC rate which is shown in Table 5.