2 Clock and Data Recovery

Clock and data recovery (CDR) is an important part of a retimer that is used to reduce the jitter that is transferred from a high-speed input to a high-speed output. This is accomplished by locking an internal voltage controlled oscillator (VCO) to the incoming data. Having an internal oscillator in phase with the input data enables the retimer to sample the data and then retransmit it.

CDR jitter transfer is limited by the phase locked loop (PLL) design. A PLL typically acts like a low-pass filter with regards to jitter. Low frequency jitter is typically passed through the CDR system, but high frequency jitter is typically removed from the CDR system. An example of CDR jitter transfers can be seen in Figure 2-1. The CDR bandwidth can typically be adjusted through retimer registers. This is detailed in the device-specific retimer programming guide. The impact of adjusting the CDR bandwidth is that the jitter transfer from input to output is also impacted. Reducing the bandwidth improves the jitter transfer, but limits the ability of the CDR system to track the input signal. Increasing the bandwidth increases the jitter transfer, but allows the CDR system to better track the input signal.

Typically, a certain frequency of data transitions is required in order to achieve CDR lock to the high-speed input. Data encoding ensures that transitions occurs even if the message being transmitted is all 0s or 1s. However, different sets of encoding results in the potential for longer runs of all 0s or all 1s. The impact of this is that a retimer designed for 64b/66b encoded data might struggle to lock to 128b/130b data. In practical implementations of TI’s retimers, data encoding is typically not a concern since the retimer is designed to meet relevant criteria of the IEEE 802.3 specification.

For additional details about CDR, see https://training.ti.com/what-is-clock-and-data-recovery.