10 High-Speed Signal Trace Impedance

As with all high-speed signals, keep total trace length for signal pairs to a minimum. The PCIe specification requires 70 to 100 Ω differential impedance. To interoperate with different root complexes and end points, Add-In-Cards require 85 Ω differential impedance. This requirement does not apply to vias, AC coupling capacitor pads, connectors, or cables. However, care needs to be taken to minimize impedance discontinuity.

Unlike high-speed differential signals for different PCIe lanes, the differential 100 MHz reference clock target impedance is 100 Ω. Additionally, the maximum allowable Random Jitter RMS is 200 fs. This is crucial in meeting the PCIe Gen5 link EQ validation test requirements.