SNLS472A January   2014  – June 2017 DS110DF1610

PRODUCTION DATA.  

  1. 1Features
  2. 2Description
  3. 3Revision History
  4. 4Pin Configuration and Functions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings (DS110DF1610)
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Characteristics
    4. 5.4 Electrical Characteristics
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Device Data Path Operation
        1. 6.3.1.1 AC-Coupled Receiver With Signal Detect
        2. 6.3.1.2 CTLE
        3. 6.3.1.3 Cross Point Switch
        4. 6.3.1.4 DFE With VGA
        5. 6.3.1.5 Clock and Data Recovery
        6. 6.3.1.6 Reference Clock
        7. 6.3.1.7 Differential Driver With FIR Filter
          1. 6.3.1.7.1 Setting the Output VOD
          2. 6.3.1.7.2 Output Driver Polarity Inversion
          3. 6.3.1.7.3 Driver Output Rise/Fall Time
      2. 6.3.2 Debug Features
        1. 6.3.2.1 Pattern Generator
        2. 6.3.2.2 Pattern Checker
        3. 6.3.2.3 Eye Opening Monitor
        4. 6.3.2.4 Interrupt Signals
      3. 6.3.3 Other Features
        1. 6.3.3.1 Lock Sequencer
    4. 6.4 Device Functional Modes
      1. 6.4.1 SMBus Slave Mode
        1. 6.4.1.1 SDA and SDC
        2. 6.4.1.2 Address Line
        3. 6.4.1.3 Device Configuration in SMBus Slave Mode
    5. 6.5 Programming
      1. 6.5.1 Bit Fields in the Register Set
      2. 6.5.2 Writing to and Reading from the Global/Shared/Channel Registers
    6. 6.6 Register Maps
      1. 6.6.1 Shared and Channel Registers
  7. 7Application and Implementation
    1. 7.1 Typical Applications
    2. 7.2 Initialization Setup
      1. 7.2.1 Data Rate Selection (Rate/Sub-Rate Table)
      2. 7.2.2 Data Rate Selection (Manual Programming)
  8. 8Power Supply Recommendations
    1. 8.1 Power Supply Filtering

8 Power Supply Recommendations

8.1 Power Supply Filtering

The power pins on the DS110DF1610 are all internally shorted together on the BGA substrate. This allows board designers to more easily distribute the bypass capacitors for power supply filtering.

Power supply filtering typically consists of a bulk 22 µF capacitor with an array of 0.1 µF capacitors all placed near the device. Additional bypass capacitors or capacitors of different values may be required depending on system conditions.
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