SNLS504E October   2015  – May 2024

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Functions
    2. 5.2 Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Power-Up Timing
    7. 6.7  Reset Timing
    8. 6.8  MII Serial Management Timing
    9. 6.9  SGMII Timing
    10. 6.10 RGMII Timing
    11. 6.11 DP83867E Start of Frame Detection Timing
    12. 6.12 DP83867IS/CS Start of Frame Detection Timing
    13. 6.13 Timing Diagrams
    14. 6.14 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 WoL (Wake-on-LAN) Packet Detection
        1. 7.3.1.1 Magic Packet Structure
        2. 7.3.1.2 Magic Packet Example
        3. 7.3.1.3 Wake-on-LAN Configuration and Status
      2. 7.3.2 Start of Frame Detect for IEEE 1588 Time Stamp
        1. 7.3.2.1 SFD Latency Variation and Determinism
          1. 7.3.2.1.1 1000Mb SFD Variation in Master Mode
          2. 7.3.2.1.2 1000Mb SFD Variation in Slave Mode
          3. 7.3.2.1.3 100Mb SFD Variation
      3. 7.3.3 Clock Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 MAC Interfaces
        1. 7.4.1.1 Serial GMII (SGMII)
        2. 7.4.1.2 Reduced GMII (RGMII)
          1. 7.4.1.2.1 1000Mbps Mode Operation
          2. 7.4.1.2.2 1000Mbps Mode Timing
          3. 7.4.1.2.3 10- and 100Mbps Mode
      2. 7.4.2 Serial Management Interface
        1. 7.4.2.1 Extended Address Space Access
          1. 7.4.2.1.1 Write Address Operation
          2. 7.4.2.1.2 Read Address Operation
          3. 7.4.2.1.3 Write (No Post Increment) Operation
          4. 7.4.2.1.4 Read (No Post Increment) Operation
          5. 7.4.2.1.5 Write (Post Increment) Operation
          6. 7.4.2.1.6 Read (Post Increment) Operation
          7. 7.4.2.1.7 Example of Read Operation Using Indirect Register Access
          8. 7.4.2.1.8 Example of Write Operation Using Indirect Register Access
      3. 7.4.3 Auto-Negotiation
        1. 7.4.3.1 Speed and Duplex Selection - Priority Resolution
        2. 7.4.3.2 Master and Slave Resolution
        3. 7.4.3.3 Pause and Asymmetrical Pause Resolution
        4. 7.4.3.4 Next Page Support
        5. 7.4.3.5 Parallel Detection
        6. 7.4.3.6 Restart Auto-Negotiation
        7. 7.4.3.7 Enabling Auto-Negotiation Through Software
        8. 7.4.3.8 Auto-Negotiation Complete Time
        9. 7.4.3.9 Auto-MDIX Resolution
      4. 7.4.4 Loopback Mode
        1. 7.4.4.1 Near-End Loopback
          1. 7.4.4.1.1 MII Loopback
          2. 7.4.4.1.2 PCS Loopback
          3. 7.4.4.1.3 Digital Loopback
          4. 7.4.4.1.4 Analog Loopback
        2. 7.4.4.2 External Loopback
        3. 7.4.4.3 Far-End (Reverse) Loopback
      5. 7.4.5 BIST Configuration
      6. 7.4.6 Cable Diagnostics
        1. 7.4.6.1 TDR
        2. 7.4.6.2 Energy Detect
        3. 7.4.6.3 Fast Link Detect
        4. 7.4.6.4 Speed Optimization
        5. 7.4.6.5 Mirror Mode
        6. 7.4.6.6 Interrupt
        7. 7.4.6.7 IEEE 802.3 Test Modes
    5. 7.5 Programming
      1. 7.5.1 Strap Configuration
      2. 7.5.2 LED Configuration
      3. 7.5.3 LED Operation From 1.8V I/O VDD Supply
      4. 7.5.4 PHY Address Configuration
      5. 7.5.5 Reset Operation
        1. 7.5.5.1 Hardware Reset
        2. 7.5.5.2 IEEE Software Reset
        3. 7.5.5.3 Global Software Reset
        4. 7.5.5.4 Global Software Restart
        5. 7.5.5.5 PCS Restart
      6. 7.5.6 Power-Saving Modes
        1. 7.5.6.1 IEEE Power Down
        2. 7.5.6.2 Deep Power-Down Mode
        3. 7.5.6.3 Active Sleep
        4. 7.5.6.4 Passive Sleep
    6. 7.6 Register Maps
      1. 7.6.1   Basic Mode Control Register (BMCR)
      2. 7.6.2   Basic Mode Status Register (BMSR)
      3. 7.6.3   PHY Identifier Register #1 (PHYIDR1)
      4. 7.6.4   PHY Identifier Register #2 (PHYIDR2)
      5. 7.6.5   Auto-Negotiation Advertisement Register (ANAR)
      6. 7.6.6   Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
      7. 7.6.7   Auto-Negotiate Expansion Register (ANER)
      8. 7.6.8   Auto-Negotiation Next Page Transmit Register (ANNPTR)
      9. 7.6.9   Auto-Negotiation Next Page Receive Register (ANNPRR)
      10. 7.6.10  1000BASE-T Configuration Register (CFG1)
      11. 7.6.11  Status Register 1 (STS1)
      12. 7.6.12  Extended Register Addressing
        1. 7.6.12.1 Register Control Register (REGCR)
        2. 7.6.12.2 Address or Data Register (ADDAR)
      13. 7.6.13  1000BASE-T Status Register (1KSCR)
      14. 7.6.14  PHY Control Register (PHYCR)
      15. 7.6.15  PHY Status Register (PHYSTS)
      16. 7.6.16  MII Interrupt Control Register (MICR)
      17. 7.6.17  Interrupt Status Register (ISR)
      18. 7.6.18  Configuration Register 2 (CFG2)
      19. 7.6.19  Receiver Error Counter Register (RECR)
      20. 7.6.20  BIST Control Register (BISCR)
      21. 7.6.21  Status Register 2 (STS2)
      22. 7.6.22  LED Configuration Register 1 (LEDCR1)
      23. 7.6.23  LED Configuration Register 2 (LEDCR2)
      24. 7.6.24  LED Configuration Register (LEDCR3)
      25. 7.6.25  Configuration Register 3 (CFG3)
      26. 7.6.26  Control Register (CTRL)
      27. 7.6.27  Testmode Channel Control (TMCH_CTRL)
      28. 7.6.28  Robust Auto MDIX Timer Configuration Register (AMDIX_TMR_CFG)
      29. 7.6.29  Fast Link Drop Configuration Register (FLD_CFG)
      30. 7.6.30  Fast Link Drop Threshold Configuration Register (FLD_THR_CFG)
      31. 7.6.31  Configuration Register 4 (CFG4)
      32. 7.6.32  RGMII Control Register (RGMIICTL)
      33. 7.6.33  RGMII Control Register 2 (RGMIICTL2)
      34. 7.6.34  SGMII Auto-Negotiation Status (SGMII_ANEG_STS)
      35. 7.6.35  100BASE-TX Configuration (100CR)
      36. 7.6.36  Viterbi Module Configuration (VTM_CFG)
      37. 7.6.37  Skew FIFO Status (SKEW_FIFO)
      38. 7.6.38  Strap Configuration Status Register 1 (STRAP_STS1)
      39. 7.6.39  Strap Configuration Status Register 2 (STRAP_STS2)
      40. 7.6.40  BIST Control and Status Register 1 (BICSR1)
      41. 7.6.41  BIST Control and Status Register 2 (BICSR2)
      42. 7.6.42  BIST Control and Status Register 3 (BICSR3)
      43. 7.6.43  BIST Control and Status Register 4 (BICSR4)
      44. 7.6.44  Configuration for Receiver's Equalizer (CRE)
      45. 7.6.45  RGMII Delay Control Register (RGMIIDCTL)
      46. 7.6.46  ANA_LD_TXG_FINE_GAINSEL_AB (ALTFGAB)
      47. 7.6.47  ANA_LD_TXG_FINE_GAINSEL_CD (ALTFGCD)
      48. 7.6.48  ANA_LD_FILTER_TUNE_AB (ALFTAB)
      49. 7.6.49  ANA_LD_FILTER_TUNE_CD (ALFTCD)
      50. 7.6.50  Configuration of Receiver's LPF (CRLPF)
      51. 7.6.51  Enable Control of Receiver's Equalizer (ECRE)
      52. 7.6.52  PLL Clock-out Control Register (PLLCTL)
      53. 7.6.53  SGMII Control Register 1 (SGMIICTL1)
      54. 7.6.54  Sync FIFO Control (SYNC_FIFO_CTRL)
      55. 7.6.55  Loopback Configuration Register (LOOPCR)
      56. 7.6.56  DSP Configuration (DSP_CONFIG)
      57. 7.6.57  DSP Feedforward Equalizer Configuration (DSP_FFE_CFG)
      58. 7.6.58  Receive Configuration Register (RXFCFG)
      59. 7.6.59  Receive Status Register (RXFSTS)
      60. 7.6.60  Pattern Match Data Register 1 (RXFPMD1)
      61. 7.6.61  Pattern Match Data Register 2 (RXFPMD2)
      62. 7.6.62  Pattern Match Data Register 3 (RXFPMD3)
      63. 7.6.63  SecureOn Pass Register 2 (RXFSOP1)
      64. 7.6.64  SecureOn Pass Register 2 (RXFSOP2)
      65. 7.6.65  SecureOn Pass Register 3 (RXFSOP3)
      66. 7.6.66  Receive Pattern Register 1 (RXFPAT1)
      67. 7.6.67  Receive Pattern Register 2 (RXFPAT2)
      68. 7.6.68  Receive Pattern Register 3 (RXFPAT3)
      69. 7.6.69  Receive Pattern Register 4 (RXFPAT4)
      70. 7.6.70  Receive Pattern Register 5 (RXFPAT5)
      71. 7.6.71  Receive Pattern Register 6 (RXFPAT6)
      72. 7.6.72  Receive Pattern Register 7 (RXFPAT7)
      73. 7.6.73  Receive Pattern Register 8 (RXFPAT8)
      74. 7.6.74  Receive Pattern Register 9 (RXFPAT9)
      75. 7.6.75  Receive Pattern Register 10 (RXFPAT10)
      76. 7.6.76  Receive Pattern Register 11 (RXFPAT11)
      77. 7.6.77  Receive Pattern Register 12 (RXFPAT12)
      78. 7.6.78  Receive Pattern Register 13 (RXFPAT13)
      79. 7.6.79  Receive Pattern Register 14 (RXFPAT14)
      80. 7.6.80  Receive Pattern Register 15 (RXFPAT15)
      81. 7.6.81  Receive Pattern Register 16 (RXFPAT16)
      82. 7.6.82  Receive Pattern Register 17 (RXFPAT17)
      83. 7.6.83  Receive Pattern Register 18 (RXFPAT18)
      84. 7.6.84  Receive Pattern Register 19 (RXFPAT19)
      85. 7.6.85  Receive Pattern Register 20 (RXFPAT20)
      86. 7.6.86  Receive Pattern Register 21 (RXFPAT21)
      87. 7.6.87  Receive Pattern Register 22 (RXFPAT22)
      88. 7.6.88  Receive Pattern Register 23 (RXFPAT23)
      89. 7.6.89  Receive Pattern Register 24 (RXFPAT24)
      90. 7.6.90  Receive Pattern Register 25 (RXFPAT25)
      91. 7.6.91  Receive Pattern Register 26 (RXFPAT26)
      92. 7.6.92  Receive Pattern Register 27 (RXFPAT27)
      93. 7.6.93  Receive Pattern Register 28 (RXFPAT28)
      94. 7.6.94  Receive Pattern Register 29 (RXFPAT29)
      95. 7.6.95  Receive Pattern Register 30 (RXFPAT30)
      96. 7.6.96  Receive Pattern Register 31 (RXFPAT31)
      97. 7.6.97  Receive Pattern Register 32 (RXFPAT32)
      98. 7.6.98  Receive Pattern Byte Mask Register 1 (RXFPBM1)
      99. 7.6.99  Receive Pattern Byte Mask Register 2 (RXFPBM2)
      100. 7.6.100 Receive Pattern Byte Mask Register 3 (RXFPBM3)
      101. 7.6.101 Receive Pattern Byte Mask Register 4 (RXFPBM4)
      102. 7.6.102 Receive Pattern Control (RXFPATC)
      103. 7.6.103 10M SGMII Configuration (10M_SGMII_CFG)
      104. 7.6.104 I/O Configuration (IO_MUX_CFG)
      105. 7.6.105 GPIO Mux Control Register (GPIO_MUX_CTRL)
      106. 7.6.106 TDR General Configuration Register 1 (TDR_GEN_CFG1)
      107. 7.6.107 TDR Peak Locations Register 1 (TDR_PEAKS_LOC_1)
      108. 7.6.108 TDR Peak Locations Register 2 (TDR_PEAKS_LOC_2)
      109. 7.6.109 TDR Peak Locations Register 3 (TDR_PEAKS_LOC_3)
      110. 7.6.110 TDR Peak Locations Register 4 (TDR_PEAKS_LOC_4)
      111. 7.6.111 TDR Peak Locations Register 5 (TDR_PEAKS_LOC_5)
      112. 7.6.112 TDR Peak Locations Register 6 (TDR_PEAKS_LOC_6)
      113. 7.6.113 TDR Peak Locations Register 7 (TDR_PEAKS_LOC_7)
      114. 7.6.114 TDR Peak Locations Register 8 (TDR_PEAKS_LOC_8)
      115. 7.6.115 TDR Peak Locations Register 9 (TDR_PEAKS_LOC_9)
      116. 7.6.116 TDR Peak Locations Register 10 (TDR_PEAKS_LOC_10)
      117. 7.6.117 TDR Peak Amplitudes Register 1 (TDR_PEAKS_AMP_1)
      118. 7.6.118 TDR Peak Amplitudes Register 2 (TDR_PEAKS_AMP_2)
      119. 7.6.119 TDR Peak Amplitudes Register 3 (TDR_PEAKS_AMP_3)
      120. 7.6.120 TDR Peak Amplitudes Register 4 (TDR_PEAKS_AMP_4)
      121. 7.6.121 TDR Peak Amplitudes Register 5 (TDR_PEAKS_AMP_5)
      122. 7.6.122 TDR Peak Amplitudes Register 6 (TDR_PEAKS_AMP_6)
      123. 7.6.123 TDR Peak Amplitudes Register 7 (TDR_PEAKS_AMP_7)
      124. 7.6.124 TDR Peak Amplitudes Register 8 (TDR_PEAKS_AMP_8)
      125. 7.6.125 TDR Peak Amplitudes Register 9 (TDR_PEAKS_AMP_9)
      126. 7.6.126 TDR Peak Amplitudes Register 10 (TDR_PEAKS_AMP_10)
      127. 7.6.127 TDR General Status (TDR_GEN_STATUS)
      128. 7.6.128 TDR Peak Sign AB (TDR_PEAK_SIGN_A_B)
      129. 7.6.129 TDR Peak Sign CD (TDR_PEAK_SIGN_C_D)
      130. 7.6.130 Programmable Gain Register (PROG_GAIN)
      131. 7.6.131 MMD3 PCS Control Register (MMD3_PCS_CTRL)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Cable Line Driver
        2. 8.2.1.2 Clock In (XI) Recommendation
        3. 8.2.1.3 Crystal Recommendations
        4. 8.2.1.4 Clock Out (CLK_OUT) Phase Noise
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 MAC Interface
          1. 8.2.2.1.1 SGMII Layout Guidelines
          2. 8.2.2.1.2 RGMII Layout Guidelines
        2. 8.2.2.2 Media Dependent Interface (MDI)
          1. 8.2.2.2.1 MDI Layout Guidelines
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Signal Traces
        2. 8.4.1.2 Return Path
        3. 8.4.1.3 Transformer Layout
        4. 8.4.1.4 Metal Pour
        5. 8.4.1.5 PCB Layer Stacking
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.2.1 SFD Latency Variation and Determinism

Time stamping packet transmission and reception using the RX_CTRL and TX_CTRL signals of RGMII is not accurate enough for latency sensitive protocols. SFD pulses offers system designers a method to improve the accuracy of packet time stamping. The SFD pulse, while varying less than RGMII signals inherently, still exhibits latency variation due to the defined architecture of 1000BASE-T. This section provides a method to determine when an SFD latency variation has occurred and how to compensate for the variation in system software to improve timestamp accuracy.

In the following section the terms baseline latency and SFD variation are used. Baseline latency is the time measured between the TX_SFD pulse to the RX_SFD pulse of a connected link partner, assuming an Ethernet cable with all 4 pairs perfectly matched in propagation time. In the scenario where all 4 pairs being perfectly matched, a 1000BASE-T PHY will not have to align the 4 received symbols on the wire and will not introduce extra latency due to alignment.

DP83867CS DP83867IS DP83867E Baseline Latency and SFD Variation in Latency Measurement Figure 7-3 Baseline Latency and SFD Variation in Latency Measurement

SFD variation is additional time added to the baseline latency before the RX_SFD pulse when the PHY must introduce latency to align the 4 symbols from the Ethernet cable. Variation can occur when a new link is established either by cable connection, auto-negotiation restart, PHY reset, or other external system effects. During a single, uninterrupted link, the SFD variation will remain constant.

The DP83867 can limit and report the variation applied to the SFD pulse while in the 1000Mb operating mode. Before a link is established in 1000Mb mode, the Sync FIFO Control Register (register address 0x00E9) must be set to value 0xDF22. The below SFD variation compensation method can only be applied after the Sync FIFO Control Register has been initialized and a new link has been established. It is acceptable to set the Sync FIFO Control register value and then perform a software restart by setting the SW_RESTART bit[14] in the Control Register (register address 0x001F) if a link is already present.
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