SNOAA62B February   2023  – October 2024 LMP7704-SP

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Overview
  5. 2SEE Mechanisms
  6. 3Test Device and Test Board Information
  7. 4Irradiation Facility and Setup
  8. 5SEL Results
  9. 6SET Results
  10. 7Extended Characterization
    1. 7.1 Correlation Test Results
    2. 7.2 Root Cause
    3. 7.3 SEL Prevention
  11. 8Summary
  12.   A Confidence Interval Calculations
  13.   B References
  14.   C Revision History

Abstract

This study characterizes the various Single-Event Effects (SEE) of heavy-ion irradiation of the LMP7704-SP. This device is a radiation-hardened, quad-channel, low offset voltage, rail-to-rail input and output (RRIO) precision amplifier with a CMOS input stage. During initial characterization, no incidences of Single-Event Latch-up (SEL) were detected up to LETEFF = 85 MeV-cm2/mg at 125°C. Single-Event Transients (SET) were detected and characterized from LETEFF 2 to 85 MeV-cm2/mg at 25°C.

Subsequent correlation testing identified a subcircuit that is vulnerable to SET, with the potential to cause device burnout under specific circuit criteria. Activation of the ESD clamping cell by a high-energy particle can lead to significant inrush current through the supply pins. Depending on the size, composition, physical distance, and parasitic resistance of the decoupling capacitors, this inrush current can be significant enough to cause localized damage, possibly resulting in a permanent high-conductance path from V+ to V–. The vulnerability can be mitigated by using relatively small (1nF-100nF) C0G decoupling capacitors at the pins, and by isolating larger (>100nF) bulk capacitors from the supply pins with series resistance. Effective shielding, including the intact package body of non-decapped units, was also shown to mitigate the vulnerability. See Extended Characterization for detailed discussion of experiments, root cause, and mitigation techniques.