10.1 Layout Guidelines

The layout of the LMG1025-Q1 is critical to its performance and functionality. The LMG1025-Q1 is available in a 2x2 DFN, which allows a low inductance connection to a FET. Figure 15shows the recommended layout of the LMG1025-Q1 with a ball-grid GaN FET.

A four-layer or higher layer count board is required to reduce the parasitic inductances of the layout to achieve suitable performance. To minimize inductance and board space, resistors and capacitors in the 0201 package should be used here. The gate drive power loss must be calculated to ensure an 0201 resistor will be able to handle the power level.