8.4.1 Repetitive SOA

The allowed repetitive SOA for the LMG341xR050 (Figure 12) is defined by the peak drain current (I_DS) and the drain to source voltage (V_DS) of the device during turn on. The peak drain current during switching is the sum of several currents going into drain terminal: the inductor current (I_ind); the current required to charge the C_OSS of the other GaN device in the totem pole; and the current required to charge the parasitic capacitance (C_par) on the switching node. 140 pF is used as an average C_OSS of the device during switching. The parasitic capacitance on the switch node may be estimated by using the overlap capacitance of the PCB. A boost topology is used for the SOA testing. The circuit shown in Figure 20 is used to generate the SOA curve in Figure 12. For reliable operation, the junction temperature of the device must also be limited to 125 °C. The I_DS of Figure 12 can be calculated by:

where drain slew rate at the peak current is estimated between 70 percent and 30 percent of the bus voltage, and C_par is the parasitic board capacitance at the switched node.

Figure 20. Circuit Used for SOA Curve in Figure 12