The high frequency and large switching currents of the LP875761-Q1 make the choice of layout important. Good power supply results only occur when care is given to correct design and layout. Layout affects noise pickup and generation and can cause a good design to perform with less-than-expected results. With a range of output currents from milliamps to 16 A and over, a good power supply layout is much more difficult than most general PCB design. Use the following steps as a reference to make sure the device is stable and keeps the correct voltage and current regulation across its intended operating voltage and current range.

• Place each CIN as close as possible to the VIN_Bx pin and the PGND_Bxx pin. Input capacitors are placed on the bottom side of the board to help with the layout routing in the example layout. Use multiple vias with a high enough current rating, and route the VIN trace wide and thick to avoid IR drops. The trace between the positive node of the input capacitor and one or more of the VIN_Bx pins of LP875761-Q1, as well as the trace between the negative node of the input capacitor and one or more of the power PGND_Bxx pins, must be kept as short as possible. The input capacitance provides a low-impedance voltage source for the switching converter. The inductance of the connection is the most important parameter of a local decoupling capacitor — parasitic inductance on these traces must be kept as small as possible to operate the device correctly. The parasitic inductance can be decreased by using a ground plane as close as possible to the top and bottom layer by using a thin dielectric layer between the top and bottom layer and the ground plane.
• The output filter, consisting of COUT and L, converts the switching signal at SW_Bx to the noiseless output voltage. It must be placed as close as possible to the device keeping the switch node small, for best EMI behavior. Route the traces between the LP875761-Q1 output capacitors and the load direct and wide to avoid losses due to the IR drop.
• Input for analog blocks (VANA and AGND) must be isolated from noisy signals. Connect VANA directly to a quiet system voltage node and AGND to a quiet ground point where no IR drop occurs. Place the decoupling capacitor as close as possible to the VANA pin.
• Connect the feedback pins FB_Bx of the LP875761-Q1 device to the respective sense pins on the processor if the processor load supports remote voltage sensing. In any case connect the feedback pin FB_B0 to the supply terminal of the point-of-load, and the feedback pin FB_B1 to the GND of the point-of-load. This compensates for the IR drop from the buck output to the point-of-load and on the GND. The sense lines are susceptible to noise, so they must be kept away from noisy signals such as PGND_Bxx, VIN_Bx, and SW_Bx, as well as high bandwidth signals such as the I²C. Avoid both capacitive and inductive coupling by keeping the sense lines short, direct, and close to each other. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane if possible. Running the signal as a differential pair is recommended for multiphase outputs.
• PGND_Bxx, VIN_Bx, and SW_Bx must be routed on thick layers. They must not surround inner signal layers, which cannot withstand interference from noisy PGND_Bxx, VIN_Bx, and SW_Bx.
• Place snubber components (capacitor and resistor) between SW_Bx and ground on all four phases if the input voltage is above 4 V. The components can be also placed to the other side of the board if there are area limitations and the routing traces can be kept short.
• Due to the small package of this converter and the overall small solution size, the thermal performance of the PCB layout is important. Many system-dependent parameters such as thermal coupling, airflow, added heat sinks, convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of a given component. A correct PCB layout, focusing on thermal performance, results in lower die temperatures. Wide and thick power traces can sink dissipated heat. This can be further improved on multilayer PCB designs with vias to different planes. This results in decreased junction-to-ambient (R_θJA) and junction-to-board (R_θJB) thermal resistances, thereby decreasing the device junction temperature, T_J. TI strongly recommends doing a careful system-level 2D or full 3D dynamic thermal analysis at the beginning of the product design process, by using a thermal modeling analysis software.