SNVA981B November   2020  – December 2024 LM61480-Q1 , LM61480T-Q1 , LM61495-Q1 , LM61495T-Q1 , LM62460-Q1

 

  1.   1
  2. 1Overview
  3. 2Functional Safety Failure In Time (FIT) Rates
  4. 3Failure Mode Distribution (FMD)
  5. 4Pin Failure Mode Analysis (Pin FMA)
  6. 5Revision History

Pin Failure Mode Analysis (Pin FMA)

This section provides a failure mode analysis (FMA) for the pins of the LM62460-Q1, LM61480(T)-Q1, and LM61495(T)-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

  • Pin short-circuited to ground (see Table 4-2)
  • Pin open-circuited (see Table 4-3)
  • Pin short-circuited to an adjacent pin (see Table 4-4)
  • Pin short-circuited to supply (see Table 4-5)

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects
ClassFailure Effects
APotential device damage that affects functionality.
BNo device damage, but loss of functionality.
CNo device damage, but performance degradation.
DNo device damage, no impact to functionality or performance.

Figure 4-1 shows the LM62460-Q1, LM61480(T)-Q1, and LM61495(T)-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the LM62460-Q1, LM61480(T)-Q1, and LM61495(T)-Q1 data sheet.

LM62460-Q1, LM61480-Q1, LM61495-Q1 LM61495T-Q1 LM61480T-Q1 Pin Diagram Figure 4-1 Pin Diagram

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground
Pin Name Pin No Description of Potential Failure Effects Failure Effect Class
PGND21Normal operation.D
VIN22VOUT = 0V.B
RBOOT3VOUT = 0V, damage if VIN > 5.5V.A
CBOOT4VOUT = 0V.B
BIAS5Normal operation.D
VCC6VOUT = 0V.B
FB7The device operates at maximum duty cycle. Output voltage rise approximately to the input voltage (VIN) level. Damage to customer load and output stage components are possible. No effect on device.B
AGND8Normal operation.D
RT9Switch frequency = 2.2MHz.C
RESET10RESET value is not valid. VOUT is normal.D
SPSP11Spread spectrum is off.C
SYNC/MODE12Mode = Auto PFM at light load. VOUT normal.C
EN13VOUT = 0V.B
VIN114VOUT = 0V.B
PGND115Normal operation.D
SW16Damage to high-side FET.A
Table 4-3 Pin FMA for Device Pins Open-Circuited
Pin Name Pin No Description of Potential Failure Effects Failure Effect Class
PGND21VOUT normal. Current loop is affected, potentially affecting noise, jitter, and EMI reliability.C
VIN22VOUT normal. All currents are in other VIN1 loop, potentially affecting noise, jitter, and EMI reliability.C
RBOOT3VOUT normal; lower efficiency and higher junction temperature.C
CBOOT4VOUT = 0V.B
BIAS5Normal operation.D
VCC6VCC output can oscillate and internal circuitry not functioning correctly is possible.B
FB7Output voltage rises to a much higher value than the programmed output voltage. Damage to customer load and output stage components are possible. No effect on device.B
AGND8Abnormal VOUT is possible due to switching noise on analog circuits.B
RT9Switch frequency can become unstable.B
RESET10RESET signal is not valid. Normal operation.C
SPSP11Spread spectrum enable or disable can be unstable.C
SYNC/MODE12Mode can switch randomly. Unpredictable behavior.C
EN13Device can shut off.B
VIN114VOUT normal. All currents are in other VIN2 loop, potentially affecting noise, jitter, EMI, reliability.C
PGND115VOUT normal. Current loop is affected, potentially affecting noise, jitter, and EMI reliability.C
SW16VOUT = 0V.B
Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin Name Pin No Shorted to Description of Potential Failure Effects Failure Effect Class
PGND2 1 VIN2 VOUT = 0V. Damage to low-side circuitry if PGND is greater than AGND. B
VIN2 2 RBOOT VOUT = 0V. B
RBOOT 3 CBOOT VOUT normal. D
CBOOT 4 BIAS VOUT = 0V. B
BIAS 5 VCC VCC ESD clamp damaged if BIAS > 5V. A
VCC 6 FB VOUT = 0V. C
FB 7 AGND The device operates at maximum duty cycle. Output voltage rise approximately to the input voltage (VIN) level. Damage to customer load and output stage components are possible. No effect on device. B
AGND 8 RT Switch frequency = 2.2MHz. C
RT 9 RESET Switch frequency can change, RT can become damaged if RESET > 5.5V. Invalid RESET is possible. B
RESET 10 SPSP Spread spectrum can enable or disable; RESET can become damaged if biased above 20V.

A

SPSP 11 SYNC/MODE Spread spectrum, sync, and mode functionality can be unstable. C
SYNC/MODE 12 EN Can disable device, change modes, or interrupt syncing. B
EN 13 VIN1 Device enabled. B
VIN1 14 PGND1 VOUT = 0V. Damage to low-side circuitry if PGND is greater than AGND. B
PGND1 15 SW VOUT = 0V. Damage to low-side circuitry if PGND is greater than AGND. B
SW 16 PGND2 Damage to high-side FET. A
Table 4-5 Pin FMA for Device Pins Short-Circuited to Supply
Pin Name Pin No Description of Potential Failure Effects Failure Effect Class
PGND21VOUT = 0V. Damage to low-side circuitry if PGND is greater than AGND.B
VIN22Normal operation.D
RBOOT3VOUT = 0V. RBOOT ESD clamp runs current to destruction.A
CBOOT4VOUT = 0V. CBOOT ESD clamp runs current to destruction.A
BIAS5If VIN exceeds 16V, damage occurs; if VIN is below 16V, normal operation.A
VCC6If VIN exceeds 5.5V, damage occurs.A
FB7If VIN exceeds 16V (fixed version), or 5.5V (adjustable version), damage occurs. VOUT = 0V.A
AGND8VOUT = 0V. Damage to other pins referred to GND.A
RT9If VIN exceeds 5.5V, damage occurs. VOUT = 0V.A
RESET10If VIN exceeds 20V, damage occurs. VOUT = 0V.A
SPSP11Spread spectrum enabled.D
SYNC/MODE12Mode set to FPWM.C
EN13Device enabled.C
VIN114Normal operation.D
PGND115VOUT = 0V. Damage to the low-side circuitry if PGND is greater than AGND.B
SW16Damage to low-side FET.A