SNVAA01 October 2020 LMR36503-Q1 , LMR36506-Q1
4 Pin Failure Mode Analysis (Pin FMA)
This section provides a Failure Mode Analysis (FMA) for the pins of the LMR36506-Q1 and LMR36503-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
- Pin short-circuited to Ground (see Table 4-2)
- Pin open-circuited (see Table 4-3)
- Pin short-circuited to an adjacent pin (see Table 4-4)
- Pin short-circuited to supply (see Table 4-5)
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
Table 4-1 TI Classification of Failure Effects
| Class | Failure Effects |
|---|---|
| A | Potential device damage that affects functionality |
| B | No device damage, but loss of functionality |
| C | No device damage, but performance degradation |
| D | No device damage, no impact to functionality or performance |
Figure 4-1 shows the LMR36506-Q1 and LMR36503-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the LMR36506-Q1 and LMR36503-Q1 data sheet.
1. See the
datasheet for more details. Pin 1 trimmed and factory-set for
externally adjustable switching frequency RT variants only.
2. Pin 1
factory-set for fixed switching frequency MODE/SYNC variants only.
3. Pin 8 trimmed
and factory-set for fixed output voltage VOUT/BIAS variants only.
4. Pin 8
factory-set for adjustable output voltage FB variants only.
Figure 4-1 Pin DiagramTable 4-2 Pin FMA for Device Pins Short-Circuited to
Ground
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| RT or MODE | 1 | Switching Frequency is 2.2 MHz | D |
| PGOOD | 2 | When not in use can be left grounded (PGOOD is not a valid signal, VOUT normal) | D |
| EN/UVLO | 3 | VOUT = 0V (Enable is off, functionality is halted) | D |
| VIN | 4 | VOUT = 0V | B |
| SW | 5 | Damage HSFET | A |
| BOOT | 6 | VOUT = 0V, HS won't turn on | B |
| VCC | 7 | VOUT = 0V | B |
| VOUT/BIAS or FB | 8 | VOUT = 0V | B |
| GND | 9 | VOUT normal | B |
Table 4-3 Pin FMA for Device Pins Open-Circuited
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| RT or MODE | 1 | If its RT part, frequency will not be defined. If it’s a MODE/SYNC part, then part could go back/forth between FPWM/PFM. Part will be up, part functional. | D |
| PGOOD | 2 | When not in use, can be left open ( PGOOD is not a valid signal, VOUT normal) | D |
| EN/UVLO | 3 | Pin cannot be left floating | B |
| VIN | 4 | VOUT = 0V | B |
| SW | 5 | VOUT = 0V | B |
| BOOT | 6 | VOUT = 0, HS won't turn on | B |
| VCC | 7 | VCC output will be unstable, can increase above 5.5V | A |
| VOUT/BIAS or FB | 8 | VOUT = 0V. Do not float this pin | C |
| GND | 9 | Vout could be abnormal, as reference voltage is not fixed | C |
Table 4-4 Pin FMA for Device Pins Short-Circuited to
Adjacent Pin
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|---|
| RT or MODE | 1 | PGOOD | If PGOOD is high, and < 5.5V Fsw = 1MHz; If PGOOD is low, Fsw = 2.2MHz .PGOOD absmax being 20V, RT ESD will damage if PG goes to 20V | A |
| PGOOD | 2 | EN/UVLO | If EN/UVLO >20 V, it will damage devices connected to PGOOD pin. | A |
| EN/UVLO | 3 | VIN | VOUT normal (Enable is on, all other blocks will work) | D |
| VIN | 4 | SW | Damage LSFET | A |
| SW | 5 | BOOT | VOUT = 0V, HS won't turn on, no Cboot | B |
| BOOT | 6 | VCC | Damage will occur, break VCC Pin | A |
| VCC | 7 | VOUT/BIAS or FB | Will not work, but no damage will occur | B |
| VOUT/BIAS or FB | 8 | GND | VOUT = 0V | B |
| GND | 9 | RT or MODE | VOUT normal if RT/MODE/SYNC pin is low, otherwise not functional | B |
Table 4-5 Pin FMA for Device Pins Short-Circuited to
supply
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| RT or MODE | 1 | If Vin > 5.5V, damage will occur. If Vin <5.5V, switching frequency is 1 MHz | A |
| PGOOD | 2 | If VIN >20 V, it will damage PGOOD | A |
| EN/UVLO | 3 | VOUT normal (Enable is on, all other blocks will work) | D |
| VIN | 4 | VOUT normal | D |
| SW | 5 | Damage LSFET | A |
| BOOT | 6 | Damage will occur, BOOT ESD clamp will be damaged | A |
| VCC | 7 | If Vin > 5.5, damage will occur | A |
| VOUT/BIAS or FB | 8 | If VIN > 20 V, damage will occur | A |
| GND | 9 | VOUT = 0V | B |