SNVS820B APRIL 2013 – December 2016
PRODUCTION DATA.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The LP5562 is designed for mobile applications with an input voltage VIN between 2.7 V to 5.5 V to support a 1S lithium-ion battery source. A microcontroller or other I2C host is required to initialize and configure the LP5562 after power-up. An internal of external 32-kHz clock is required. If multiple LP5562 devices are used to sequence multiple RGB LEDs, then the external 32-kHz clock input is required. The ADDRSEL0 and ADDRSEL1 pins can be used to allow unique sequencing of up to four LP5562 devices on the same I2C bus.
The four LED current drivers can be configured up to 25.5-mA LED current each and are tolerant up to 6-V LED supply voltage.
Figure 44 shows the typical application for LP5562 supporting one RGB LED and one White LED with the four LED current outputs.
For typical LED-driver applications, use the parameters listed in Table 44.
DESIGN PARAMETER | EXAMPLE VALUE |
---|---|
Minimum input voltage | 2.7 V |
Maximum input voltage | 5.5 V |
EN/VCC logic level | 1.8 V |
R output current | 24 mA |
G output current | 20 mA |
B output current | 22 mA |
WLED output current | 18 mA |
PWM frequency | 256 Hz |
32-kHz clock source | External |
Light engines 1, 2 and 3 | Blink on/off |
Power-save mode | Enabled |
MODEL | TYPE | VENDOR | VOLTAGE RATING | SIZE INCH (MM) |
---|---|---|---|---|
1 µF for CIN | ||||
C1005X5R1A105K | Ceramic X5R | TDK | 10 V | 0402 (1005) |
GRM155R61A105KE15D | Ceramic X5R | Murata | 10 V | 0402 (1005) |
LEDs | User Defined |
To set the PWM frequency to 256 Hz the PWM_HF bit must be written to '0'. It is located at register address 0x08 bit 6.
To set the clock source to external clock input the INT_CLK_EN and CLK_DET_EN bits are set to “00”. These are located at register address 0x08 bits 0 and 1.
To enable the power save mode function the PWRSAVE_EN bit must be set to '1'. It is located at register address 0x08 bit 5.
Sample code for 100% to 0% duty blinking LED function is shown in Table 46.
ADDRESS | VALUE | COMMENTS | |
---|---|---|---|
Engine 1 Section Start | |||
0 | 40FF | Loop1 | set_pwm 255 |
1 | 4D00 | wait 200 | |
2 | 4000 | set_pwm 0 | |
3 | 6000 | wait 500 | |
4 | A200 | branch 4, loop1 | |
5 | D000 | end, i | |
Engine 2 Section Start | |||
10 | 40FF | Loop2 | set_pwm 255 |
11 | 4D00 | wait 200 | |
12 | 4000 | set_pwm 0 | |
13 | 6000 | wait 500 | |
14 | A290 | branch 5, loop2 | |
15 | D000 | end, i | |
Engine 3 Section Start | |||
20 | 40FF | Loop3 | set_pwm 255 |
21 | 4D00 | wait 200 | |
22 | 4000 | set_pwm 0 | |
23 | 6000 | wait 500 | |
24 | A320 | branch 6, loop3 | |
25 | D000 | end, i |
External Clock | PS. Blink-Program | |