SNVSA02A January   2016  – December 2016

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High Voltage Start-up Regulator
      2. 7.3.2  VCC Regulator
      3. 7.3.3  Oscillator
      4. 7.3.4  SYNIN and SYNOUT
      5. 7.3.5  Enable
      6. 7.3.6  Power Good
      7. 7.3.7  Output Voltage
      8. 7.3.8  Minimum Output Voltage Adjustment
      9. 7.3.9  Current Sense
      10. 7.3.10 DCR Current Sensing
      11. 7.3.11 Error Amplifier and PWM Comparator
      12. 7.3.12 Slope Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Hiccup Mode Current Limiting
      2. 7.4.2 Standby Mode
      3. 7.4.3 Soft Start
      4. 7.4.4 Diode Emulation
      5. 7.4.5 High and low-side Drivers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Inductor Calculation
        2. 8.2.2.2  Current Sense Resistor
        3. 8.2.2.3  Output Capacitor
        4. 8.2.2.4  Input Filter
        5. 8.2.2.5  EMI Filter Design
        6. 8.2.2.6  MOSFET Selection
        7. 8.2.2.7  Driver Slew Rate Control
        8. 8.2.2.8  Sub-Harmonic Oscillation
        9. 8.2.2.9  Control Loop
        10. 8.2.2.10 Error Amplifier
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

RWG Package
40-Pin VQFN
Top View
LM5140-Q1 po_snvsa02.gif
Connect Exposed Pad on bottom to AGND and PGND on the PCB.

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
1 SS2 I Channel 2 soft-start programming pin. An external capacitor and an internal 20-μA current source set the ramp rate of the internal error amplifier reference during soft-start. Pulling SS pin below 80 mV turns off the channel 2 gate driver outputs, but all the other functions remain active.
2 COMP2 O Output of the channel 2 transconductance error amplifier.
3 FB2 I Feedback input of channel 2. Connect the FB2 pin to VDD for a 5-V output or connect FB2 to ground for a fixed 8-V output. A resistive divider from the VOUT2 to the FB2 pin sets the output voltage level between 1.5 V and 15 V. The regulation threshold at the FB2 pin is 1.2 V.
4 CS2 I Channel 2 current sense amplifier input. Make a low current Kelvin connection between this pin and the inductor side of the external current sense resistor.
5 VOUT2 I Output and the current sense amplifier input of channel 2 . Connect this pin to the output side of the channel 2 current sense resistor.
6 VCCX I Optional input for an external bias supply. If VCCX > 4.5 V, VCCX is internally connected to VCC and the internal VCC regulator is disabled. If VCCX is unused, it must be grounded.
7 PG2 O An open-collector output which goes low if VOUT2 is outside a specified regulation window.
8 HOL2 O Channel 2 high-side gate driver turnoff output.
9 HO2 O Channel 2 high-side gate driver turnon output.
10 SW2 I Switching node of the channel 2 buck regulator. Connect to the bootstrap capacitor, the source terminal of the high-side MOSFET and the drain terminal of the low-side MOSFET.
11 HB2 O Channel 2 high-side driver supply for bootstrap gate drive.
12 LOL2 O Channel 2 low-side gate driver turnoff output.
13 LO2 O Channel 2 low-side gate driver turnon output.
14 PGND2 G Power ground connection pin for low-side NMOS gate driver.
15 VCC P VCC bias supply pin. Pin 15 and pin 16 must to be connected together on the PCB.
16 VCC P VCC bias supply pin. Pin 15 and pin 16 must to be connected together on the PCB.
17 PGND1 G Power ground connection pin for low-side NMOS gate driver.
18 LO1 O Channel 1 low-side gate driver turnon output.
19 LOL1 O Channel 1 low-side gate driver turnoff output.
20 HB1 O Channel 1 high-side driver supply for bootstrap gate drive.
21 SW1 I Switching node of the channel 1 buck regulator. Connect to the bootstrap capacitor, the source terminal of the high-side MOSFET and the drain terminal of the low-side MOSFET.
22 HO1 O Channel 1 high-side gate driver turnon output
23 HOL1 O Channel 1 high-side gate driver turnoff output.
24 PG1 O An open-collector output which goes low if VOUT1 is outside a specified regulation window.
25 VIN P Supply voltage input source for the VCC regulators.
26 VOUT1 I VOUT1 and current sense amplifier input of channel 1. Connect to the output side of the channel 1 current sense resistor.
27 CS1 I Channel 1 current sense amplifier input. Make a low current Kelvin connection between this pin and the inductor side of the external current sense resistor.
28 FB1 I Feedback input of channel 1. Connect the FB1 pin to VDDA for a 3.3-V output or connect FB1 to ground for a 5-V output. A resistive divider from the VOUT1 to the FB1 pin sets the output voltage level between 1.5 V and 15 V. The regulation threshold at the FB1 pin is 1.2 V.
29 COMP1 O Output of the channel 1 transconductance error amplifier.
30 SS1 I Channel 2 soft-start programming pin. An external capacitor and an internal 20-μA current source set the ramp rate of the internal error amplifier reference during soft-start. Pulling SS pin below 80 mV turns off the channel 1 gate driver outputs, but the all the other function remain active.
31 EN1 I An active high logic input enables channel 1.
32 RES O Restart timer pin. An external capacitor configures the hiccup mode current limiting. The capacitor at the RES pin determines the time the controller remains off before automatically restarting in hiccup mode. The two regulator channels operate independently. One channel may operate in normal mode while the other is in hiccup mode overload protection. The hiccup mode commences when either channel experiences 512 consecutive PWM cycles with cycle-by-cycle current limiting. Connect the RES pin to VDD during power up to disable hiccup mode protection.
33 DEMB I Diode Emulation pin. If the DEMB pin is grounded, diode emulation is enabled. If it is connected to VDDA the LM5140-Q1 operates in FPWM mode with continuous conduction at light loads.
34 ILSET I Current Limit Threshold pin. Connecting the ILSET pin to VDDA sets the current limit threshold to 73 mV for channel 1 and channel 2.
Connecting the ILSET pin to GND sets the current limit thresholds to 48 mV.
35 AGND G Analog ground connection. Ground return for the internal voltage reference and analog circuits.
36 VDDA P Internal analog bias regulator output. Connect a capacitor from the VDDA pin the AGND.
37 OSC I Frequency selection pin. Connecting the OSC pin to VDDA selects the default oscillator frequency of 2.2 MHz. Connecting the OSC pin to ground sets frequency to 440 kHz.
38 SYNIN I Sync input pin. The internal oscillator can be synchronized to an external clock. If the synchronization feature is not used, the SYNIN pin must be connected to AGND.
39 SYNOUT O Sync output pin. The TTL level output signal is 180º out of phase with the HO1 gate drive of channel 1.
40 EN2 I An active high logic input enables channel 2.
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