8.3.3 Manual Reset (MR) Input

The manual reset (MR) input allows a processor GPIO or other logic circuits to initiate a reset. A logic low on MR with pulse duration longer than t_{MR_RES} will causes reset output to assert. After MR returns to a logic high (V_{MR_H}) and VDD is above V_IT+, reset is deasserted after the user programmed reset time delay (t_D) expires.

If MR is not controlled externally, then MR can be left disconnected. If the logic signal controlling MR is less than VDD, then additional current flows from VDD into MR internally. For minimum current consumption, drive MR to either VDD or GND. V_MR should not be higher than VDD voltage.

Figure 47. Timing Diagram MR and RESET (TPS3840DL)