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SNVSB03D December 2018 – January 2020

PRODUCTION DATA.

7.6 Timing Requirements

At 1.5 V ≤ V_DD ≤ 10 V, CT = MR = Open, RESET pull-up resistor (R_pull-up) = 100 kΩ to VDD, output reset load (C_LOAD) = 10 pF and over the operating free-air temperature range – 40°C to 125°C, VDD slew rate < 100mV / us, unless otherwise noted. Typical values are at T_J = 25°C.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_STRT	Startup Delay⁽¹⁾	CT pin open	100	220	350	µs
t_{P_HL}	Propagation detect delay for VDD falling below V_IT-	V_DD= V_IT+to (V_IT-) - 10%⁽²⁾		15	30	µs
t_D	Reset time delay⁽³⁾	CT pin = open			50	µs
		CT pin = 10 nF		6.2		ms
		CT pin = 1 µF		619		ms
t_{GI_VIT-}	Glitch immunity V_IT-	5% V_IT- overdrive⁽⁴⁾		10		µs
t_{MR_PW}	MR pin pulse duration to initiate reset			300		ns
t_{MR_RES}	Propagation delay from MR low to reset	V_DD = 4.5 V, MR < V_{MR_L}		700		ns
t_{MR_tD}	Delay from release MR to deasert reset	V_DD = 4.5 V, MR = V_{MR_L}to V_{MR_H}		t_D		ms

(1) When VDD starts from less than the specified minimum V_DD and then exceeds V_IT+, reset is release after the startup delay (t_STRT), a capacitor at CT pin will add t_D delay to t_STRT time

(2) t_{P_HL} measured from threhold trip point (V_IT-) to V_OL for active low variants and V_OH for active high variants.

(3) The MIN and MAX reset time delay with external capacitor depends on R_CTand is calculated using Equation 5 and Equation 6 in Section 8.3.2

(4) Overdrive % = [(V_DD/ V_IT-) - 1] × 100%

1. t_D_{(no cap)} is included in t_STRT time delay. If t_D delay is programmed by an external capacitor connected to CT pin then t_D programmed time will be added to the startup time, VDD slew rate = 100 mV / µs.

2. Open-Drain timing diagram assumes pull-up resistor is connected to RESET

3. RESET output is undefined when VDD is < V_POR

Figure 4. Timing Diagram TPS3840DL (Open-Drain Active-Low)

1. t_D_{(no cap)} is included in t_STRT time delay. If t_D delay is programmed by an external capacitor connected to CT pin, then t_D programmed time will be added to the startup time. VDD slew rate = 100 mV / µs.

2. RESET output is undefined when VDD < V_POR and limited to V_OL for VDD slew rate = 100 mV / µs

Figure 5. Timing Diagram TPS3840PL (Push-Pull Active-Low)

1. t_D_{(no cap)} is included in t_STRT time delay. If t_D delay is programmed by an external capacitor connected to CT pin, then t_D programmed time will be added to the total startup time. VDD slew rate = 100 mV / µs.

Figure 6. Timing Diagram TPS3840PH (Push-Pull Active-High)