The LM26420-Q1 is designed to operate from an input voltage supply range between 3 V and 5.5 V. This input supply must be well regulated and able to withstand maximum input current and maintain a stable voltage. The resistance of the input supply rail must be low enough that an input current transient does not cause a high enough drop at the LM26420-Q1 supply voltage that can cause a false UVLO fault triggering and system reset. If the input supply is located more than a few inches from the LM26420-Q1, additional bulk capacitance can be required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 47-μF or 100-μF electrolytic capacitor is a typical choice.

The LM26420-Q1 contains a high-side PMOS FET and a low-side NMOS FET as shown in Figure 42. The source nodes of the high-side PMOS FETs are connected to VIND₁ and VIND₂, respectively. VINC is the power source for the high-side and low-side gate drivers. Ideally, VINC is connected to VIND₁ and VIND₂ by an RC filter as detailed in VINC Filtering Components. If VINC is allowed to be lower than VIND₁ or VIND₂, the high-side PMOS FETs can be turned on regardless of the state of the respective gate drivers. Under this condition, shoot through will occur when the low-side NMOS FET is turned on and permanent damage can result. When applying input voltage to VINC, VIND₁, and VIND₂, VINC must not be less than VIND_1,2 – V_TH to avoid shoot through and FET damage.

Figure 42. VINC, VIND₁, and VIND₂ Connection