SNVU543A November   2016  – December 2016 LM5170 , LM5170-Q1

 

  1.   LM5170-Q1 EVM User Guide
    1.     Trademarks
    2. 1 Features and Electrical Performance
    3. 2 Setup
      1. 2.1 EVM Configurations
      2. 2.2 Bench Setup
      3. 2.3 Test Equipment
    4. 3 Test Procedure
      1. 3.1 Buck Mode Power-Up and Power-Down Sequence
      2. 3.2 Boost Mode Power-Up and Power-Down Sequence
      3. 3.3 Bidirectional Operation Power-Up and Power-Down Sequence
      4. 3.4 Operating the EVM With the Onboard Analog Loop Control Circuit
      5. 3.5 Operating the EVM With External MCU or Other Digital Circuit
    5. 4 Test Data
      1. 4.1  Efficiency
      2. 4.2  Current Regulation and Monitoring
      3. 4.3  Typical Master Enable Power Up and Shutdown
      4. 4.4  Channel Enable and Disable
      5. 4.5  Dual-Channel Interleaving Operation
      6. 4.6  ISETA Tracking
      7. 4.7  Diode Emulation Preventing Negative Currents
      8. 4.8  Dynamic DIR Change
      9. 4.9  Step Load Response
      10. 4.10 OVP
      11. 4.11 Output Short Circuit
    6. 5 Design Files
      1. 5.1 Schematics
      2. 5.2 Bill of Materials
      3. 5.3 Board Layout
  2.   Revision History

Board Layout

The EVM includes various headers for flexible configurations suitable for different applications. Figure 32 through Figure 41 show the EVM PCB artwork.

pcb_layer_01_silk_screen_top_snvu543.pngFigure 32. EVM Top Layer Silkscreen
pcb_layer_01_copper_top_snvu543.pngFigure 33. EVM Top Layer Copper
pcb_inner_layer_01_snvu543.pngFigure 34. EVM Middle Layer 1
pcb_inner_layer_02_snvu543.pngFigure 35. EVM Middle Layer 2
pcb_layer_05_inner_layer_3_snvu543.pngFigure 36. EVM Middle Layer 3
pcb_layer_06_inner_layer_4_snvu543.pngFigure 37. EVM Middle Layer 4
pcb_inner_layer_05_snvu543.pngFigure 38. EVM Middle Layer 5
pcb_layer_08_inner_layer_6_snvu543.pngFigure 39. EVM Middle Layer 6
pcb_layer_09_bottom_layer_snvu543.pngFigure 40. EVM Bottom Layer Copper
pcb_layer_10_silk_screen_bottom_snvu543.pngFigure 41. EVM Bottom Layer Silkscreen