SNVU860 april 2023 LP87523-Q1

1 Introduction

This technical reference manual can be used as a reference for the LP875230D-Q1 default register bits after power up. This technical reference manual does not provide information about the electrical characteristics, external components, package, or the functionality of the device. For this information and the full register map, refer to the LP8752x-Q1 Four-Phase 10-A Buck Converter With Integrated Switches data sheet data sheet.

Table 1-1 provides the quick overview of each regulator default OTP settings. Section 2 provides an overview of default power up and power down sequence. Table 3-1 lists all the default OTP settings after power up.

Table 1-1 Main OTP Settings for regulators

Description		Bit Name	Value
Device identification	OTP configuration	OTP_ID	E4h
BUCK0+BUCK1 (2-phase operation)	Output voltage	BUCK0_VSET	800 mV
	Enable (ENx pin or I²C register write)	EN_BUCK0, EN_PIN_CTRL0, BUCK0_EN_PIN_SELECT	EN1 pin
	Startup delay	BUCK0_STARTUP_DELAY	6 ms
	Shutdown delay	BUCK0_SHUTDOWN_DELAY	0 ms
	Force PWM	BUCK0_FPWM	Forced PWM
	Force multiphase	BUCK0_FPWM _MP	Forced multi-phase operation
	Peak current limit	ILIM0, ILIM1	4.5 A
	Maximum load current	N/A	7 A
	Slew rate	N/A	3.8 mV/us
BUCK2	Output voltage	BUCK2_VSET	1200 mV
	Enable (ENx pin or I²C register write)	EN_BUCK2, EN_PIN_CTRL2, BUCK2_EN_PIN_SELECT	EN1 pin
	Startup delay	BUCK2_STARTUP_DELAY	4 ms
	Shutdown delay	BUCK2_SHUTDOWN_DELAY	2 ms
	Force PWM	BUCK2_FPWM	Forced PWM
	Peak current limit	ILIM2	3.0 A
	Maximum load current	N/A	2 A
	Slew rate	N/A	3.8 mV/us
BUCK3	Output voltage	BUCK3_VSET	1800 mV
	Enable (ENx pin or I²C register write)	EN_BUCK3, EN_PIN_CTRL3, BUCK3_EN_PIN_SELECT	EN1 pin
	Startup delay	BUCK3_STARTUP_DELAY	2 ms
	Shutdown delay	BUCK3_SHUTDOWN_DELAY	4 ms
	Force PWM	BUCK3_FPWM	Forced PWM
	Peak current limit	ILIM3	2.0 A
	Maximum load current	N/A	1 A
	Slew rate	N/A	3.8 mV/us
Spread spectrum		EN_SPREAD_SPEC	ENABLED
Switching frequency		N/A	2 MHz
I²C address		N/A	60h