SNVU865 june 2023 LP87702-Q1

1 Introduction

This Technical Reference Manual can be used as a reference for the LP8770-Q1 default register bits after OTP memory download. This Technical Reference Manual does not provide information about the electrical characteristics, external components, package, or the functionality of the device. For this information and the full register map, refer to the LP87702-Q1 Dual Buck Converter and 5-V Boost With Diagnostic Functions data sheet and LP877020-Q1 Configuration Guide.

Main OTP settings for power rails are listed in Table 1-1. Full list of register bits loaded from OTP memory is shown in Section 2.

Table 1-1 Main OTP Settings for Power Rails

	DESCRIPTION	BIT NAME	LP877021
Device Identification	OTP configuration	OTP_ID	38
Device Identification	Revision for OTP_ID	OTP_REV	1
BUCK0	Output voltage	BUCK0_VSET	1.8V
	Enable, EN-pin or I²C register	BUCK0_EN_PIN_CTRL, BUCK0_EN	EN1
	Force PWM	BUCK0_FPWM	Yes
	Peak current limit	BUCK0_ILIM	4 A
	Maximum load current	N/A	3 A
BUCK1	Output voltage	BUCK1_VSET	1.1V
	Enable, EN-pin or I²C register	BUCK1_EN_PIN_CTRL, BUCK1_EN	EN1
	Force PWM	BUCK1_FPWM	Yes
	Peak current limit	BUCK1_ILIM	4.5 A
	Maximum load current	N/A	3.5 A
BOOST	Mode, boost or bypass	Mode control bit is not in customer register space	Boost
	Output voltage	BOOST_VSET	5 V
	Enable, EN-pin or I²C register	BOOST_EN_PIN_CTRL, BOOST_EN	NRST
	Peak current limit	BOOST_ILIM0, BOOST_ILIM1	1.4A
	Maximum load current	N/A	0.6 A
VANA	VANA over-voltage threshold	VANA_OVP_SEL (selection bit is not in customer register space)	4.3V rising

There are a few important connections to ensure the LP877021-Q1 is configured correctly. Good example of how to connect the LP877021-Q1 PMIC is shown in Figure 1-1 .

Figure 1-1 Typical Connection to LP877021-Q1