SPMA082 August 2021 TM4C1230C3PM , TM4C1230D5PM , TM4C1230E6PM , TM4C1230H6PM , TM4C1231C3PM , TM4C1231D5PM , TM4C1231D5PZ , TM4C1231E6PM , TM4C1231E6PZ , TM4C1231H6PGE , TM4C1231H6PM , TM4C1231H6PZ , TM4C1232C3PM , TM4C1232D5PM , TM4C1232E6PM , TM4C1232H6PM , TM4C1233C3PM , TM4C1233D5PM , TM4C1233D5PZ , TM4C1233E6PM , TM4C1233E6PZ , TM4C1233H6PGE , TM4C1233H6PM , TM4C1233H6PZ , TM4C1236D5PM , TM4C1236E6PM , TM4C1236H6PM , TM4C1237D5PM , TM4C1237D5PZ , TM4C1237E6PM , TM4C1237E6PZ , TM4C1237H6PGE , TM4C1237H6PM , TM4C1237H6PZ , TM4C123AE6PM , TM4C123AH6PM , TM4C123BE6PM , TM4C123BE6PZ , TM4C123BH6PGE , TM4C123BH6PM , TM4C123BH6PZ , TM4C123BH6ZRB , TM4C123FE6PM , TM4C123FH6PM , TM4C123GE6PM , TM4C123GE6PZ , TM4C123GH6PGE , TM4C123GH6PM , TM4C123GH6PZ , TM4C123GH6ZRB , TM4C1290NCPDT , TM4C1290NCZAD , TM4C1292NCPDT , TM4C1292NCZAD , TM4C1294KCPDT , TM4C1294NCPDT , TM4C1294NCZAD , TM4C1297NCZAD , TM4C1299KCZAD , TM4C1299NCZAD , TM4C129CNCPDT , TM4C129CNCZAD , TM4C129DNCPDT , TM4C129DNCZAD , TM4C129EKCPDT , TM4C129ENCPDT , TM4C129ENCZAD , TM4C129LNCZAD , TM4C129XKCZAD , TM4C129XNCZAD
Frame rate is the frequency at which consecutive frames appear on a display. The maximum frame rate is determined by the image size in combination with the pixel clock rate. More precisely, the pixel clock frequency, the size of the display, and the porch intervals determine the frame rate. The porch intervals that are expressed in terms of pixel clocks refer to the blanking period between each line and each frame. For the duration required for the porch intervals, see the device-specific data sheet. The FPS can be expressed as:
FPS = Fpixel_clock / ((HBP +
Resolution Width + HFP) x (VBP + Resolution Height + VFP))
Suppose the following example:
Pixel clock = 60 MHz LCD
clock
(This is the maximum LCD clock on TM4C129 MCU.)
LCD Controller mode = parallel RGB
interface (24-bit bus)
Color depth = 24-bit
Resolution = QXGA (2048 x
1536)
Porch intervals = Assume
insignificant compared to the resolution width and height
FPS = 60 MHz / (2048 x 1536) = 19
or less if porch intervals is taken into consideration
For video playback, normally a minimum of 24FPS is needed for human eyes to render the motion smoothly. Therefore, there is a compromise between FPS, display resolution, and color depth when choosing the optimal displays to use.
Suppose another example using a SPI interface:
Pixel clock = 60 MHz SPI
clock
(This is the maximum SPI clock on TM4C129 MCU.)
LCD Controller mode = SPI
Interface
Color depth = 24-bit
Resolution = QVGA (320 x
240)
Porch intervals = Assume
insignificant compared to the resolution width and height
FPS = 60 MHz / (2048 x 2048 x 24)
= 35 or less if porch intervals is taken into consideration
Theoretically, it is possible to support a small display with video playback at greater than 24 FPS.