An important element of managing an RTOS on a microcontroller is correctly handling the use of hardware interrupts from the microcontroller without disrupting the RTOS kernel and scheduler. Because FreeRTOS aims to be chip and compiler agonistic, there is no unique plug-in for device specific hardware interrupts. Instead, hardware interrupt processing occurs outside of the kernel and scheduler and must be handled by using very lean interrupt service routines (ISRs). Minimizing the cycles spent executing the ISR will allow the scheduler to take control of the application quicker.

Because most ISRs require the processing of a specific event that has been triggered, the FreeRTOS kernel provides methods to defer the processing of events from an ISR to a task that is part of the kernel and runs according to the scheduler. These deferred tasks have configured priorities that allow developers the same flexibility as ISR processing where priorities can be set to ensure the most important interrupts are processed first. With this method, the hardware ISR processing can be minimalized while still retaining priorities as required by an application.

To learn more details about deferred interrupt processing as well as FreeRTOS interrupt safe API and how context switching is performed by the kernel, see the Interrupt Management chapter in Mastering the FreeRTOS Real Time Kernel.

From a TM4C microcontroller perspective, configuring interrupts includes mapping the ISR to the interrupt vector table so that the ISR is executed whenever the hardware interrupt is triggered. There are two methods to correctly register a new interrupt to the interrupt vector table. These are both documented in full detail in the TivaWare Vector Tables and IntDefaultHandler section of the Getting Started with TivaWare™ User's Guide.