SPNS183C September 2012 – June 2015
PRODUCTION DATA.
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Supply voltage range: | VCC(2) | -0.3 | 1.43 | V | |
VCCIO, VCCP(2) | -0.3 | 4.6 | V | ||
VCCAD | -0.3 | 6.25 | V | ||
Input voltage range: | All input pins, with exception of ADC pins | -0.3 | 4.6 | V | |
ADC input pins | -0.3 | 6.25 | V | ||
Input clamp current: | IIK (VI < 0 or VI > VCCIO) All pins, except AD1IN[23:0] or AD2IN[15:0] |
-20 | +20 | mA | |
IIK (VI < 0 or VI > VCCAD) AD1IN[23:0] or AD2IN[15:0] |
-10 | +10 | mA | ||
Total | -40 | +40 | mA | ||
Operating free-air temperature range, TA: | -40 | 105 | °C | ||
Operating junction temperature range, TJ: | -40 | 130 | °C | ||
Storage temperature range, Tstg | -65 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
VESD | Electrostatic discharge (ESD) performance: | Human body model (HBM), per ANSI/ESDA/JEDEC JS001(1) | ±2 | kV | |
Charged device model (CDM), per JESD22-C101(2) | All pins | ±250 | V |
NOMINAL CORE VOLTAGE (VCC) | JUNCTION TEMPERATURE (Tj) |
LIFETIME POH |
---|---|---|
1.2 | 105ºC | 100K |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VCC | Digital logic supply voltage (Core) | 1.14 | 1.2 | 1.32 | V | |
VCCPLL | PLL Supply Voltage | 1.14 | 1.2 | 1.32 | V | |
VCCIO | Digital logic supply voltage (I/O) | 3 | 3.3 | 3.6 | V | |
VCCAD | MibADC supply voltage | 3 | 5.25 | V | ||
VCCP | Flash pump supply voltage | 3 | 3.3 | 3.6 | V | |
VSS | Digital logic supply ground | 0 | V | |||
VSSAD | MibADC supply ground | -0.1 | 0.1 | V | ||
VADREFHI | A-to-D high-voltage reference source | VSSAD | VCCAD | V | ||
VADREFLO | A-to-D low-voltage reference source | VSSAD | VCCAD | V | ||
VSLEW | Maximum positive slew rate for VCCIO, VCCAD and VCCP supplies | 1 | V/µs | |||
TA | Operating free-air temperature | -40 | 105 | °C | ||
TJ | Operating junction temperature(2) | -40 | 130 | °C |
As shown in the figure above, the TCM RAM can support program and data fetches at full CPU speed without any address or data wait states required.
The TCM flash can support zero address and data wait states up to a CPU speed of 50 MHz in nonpipelined mode. The flash supports a maximum CPU clock speed of 200 MHz in pipelined mode with one address wait state and three data wait states.
The flash wrapper defaults to non-pipelined mode with zero address wait state and one random-read data wait state.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
ICC | VCC digital supply current (operating mode) fVCLK = fHCLK/2; Flash in pipelined mode; VCCmax |
fHCLK = 200MHz | 205(3) | 340(1) | mA | ||
VCC Digital supply current (LBIST/PBIST mode) |
LBIST/PBIST clock frequency = 100MHz |
265(3) | 455(2)(4) | mA | |||
ICCPLL | VCCPLL digital supply current (operating mode) | VCCPLL = VCCPLLmax | 10 | mA | |||
ICCIO | VCCIO Digital supply current (operating mode. | No DC load, VCCmax | 10 | mA | |||
ICCAD | VCCAD supply current (operating mode) | Single ADC operational, VCCADmax | 15 | mA | |||
Both ADCs operational, VCCADmax | 30 | ||||||
IADREFHI | ADREFHI supply current (operating mode) | Single ADC operational, ADREFHImax | 3 | mA | |||
Both ADCs operational, ADREFHImax | 6 | ||||||
ICCP | VCCP supply current | read from 1 bank and program another bank, VCCPmax | 55 | mA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
Vhys | Input hysteresis | All inputs | 180 | mV | |||
VIL | Low-level input voltage | All inputs | -0.3 | 0.8 | V | ||
VIH | High-level input voltage | All inputs | 2 | VCCIO + 0.3 | V | ||
VOL | Low-level output voltage | IOL = IOLmax | 0.2 VCCIO | V | |||
IOL = 50 µA, standard output mode | 0.2 | ||||||
IOL = 50 µA, low-EMI output mode (see Section 5.13) | 0.2 VCCIO | ||||||
VOH | High-level output voltage | IOH = IOHmax | 0.8 VCCIO | V | |||
IOH = 50 µA, standard output mode | VCCIO -0.3 | ||||||
IOH = 50 µA, low-EMI output mode (see Section 5.13) | 0.8 VCCIO | ||||||
IIK | Input clamp current (I/O pins)(2) | VI < VSSIO - 0.3 or VI > VCCIO + 0.3 | -3.5 | 3.5 | mA | ||
II | Input current (I/O pins) | IIH Pulldown 20µA | VI = VCCIO | 5 | 40 | µA | |
IIH Pulldown 100µA | VI = VCCIO | 40 | 195 | ||||
IIL Pullup 20µA | VI = VSS | -40 | -5 | ||||
IIL Pullup 100µA | VI = VSS | -195 | -40 | ||||
All other pins | No pullup or pulldown | -1 | 1 | ||||
CI | Input capacitance | 2 | pF | ||||
CO | Output capacitance | 3 | pF |
Table 5-2 shows the thermal resistance characteristics for the QFP - PGE mechanical package.
Table 5-3 shows the thermal resistance characteristics for the BGA - ZWT mechanical package.
LOW-LEVEL OUTPUT CURRENT, IOL for VI=VOLmax or HIGH-LEVEL OUTPUT CURRENT, IOH for VI=VOHmin |
SIGNALS |
---|---|
8 mA |
MIBSPI5CLK, MIBSPI5SOMI[0], MIBSPI5SOMI[1], MIBSPI5SOMI[2], MIBSPI5SOMI[3], MIBSPI5SIMO[0], MIBSPI5SIMO[1], MIBSPI5SIMO[2], MIBSPI5SIMO[3], TMS, TDI, TDO, RTCK, SPI4CLK, SPI4SIMO, SPI4SOMI, nERROR, N2HET2[1], N2HET2[3], N2HET2[5], N2HET2[7], N2HET2[9], N2HET2[11], N2HET2[13], N2HET2[15] ECAP1, ECAP4, ECAP5, ECAP6 EQEP1I, EQEP1S, EQEP2I, EQEP2S EPWM1A, EPWM1B, EPWM1SYNCO, ETPW2A, EPWM2B, EPWM3A, EPWM3B, EPWM4A, EPWM4B, EPWM5A, EPWM5B, EPWM6A, EPWM6B, EPWM7A, EPWM7B EMIF_ADDR[0:12], EMIF_BA[0:1], EMIF_CKE, EMIF_CLK, EMIF_DATA[0:15], EMIF_nCAS, EMIF_nCS[0:4], EMIF_nDQM[0:1], EMIF_nOE, EMIF_nRAS, EMIF_nWAIT, EMIF_nWE, EMIF_RNW MDCLK, MDIO, MII_RX_VCLKA4, MII_TX_VCLKA4, MII_TXD[0:3], MII_TXEN, RMII_REFCLK, RMII_TXD[0:1], RMII_TXEN |
4 mA |
TEST, MIBSPI3SOMI, MIBSPI3SIMO, MIBSPI3CLK, MIBSPI1SIMO, MIBSPI1SOMI, MIBSPI1CLK, ECAP2, ECAP3 nRST |
2 mA zero-dominant |
AD1EVT, CAN1RX, CAN1TX, CAN2RX, CAN2TX, CAN3RX, CAN3TX, GIOA[0-7], GIOB[0-7], LINRX, LINTX, MIBSPI1nCS[0], MIBSPI1nCS[1-3], MIBSPI1nENA, MIBSPI3nCS[0-3], MIBSPI3nENA, MIBSPI5nCS[0-3], MIBSPI5nENA, N2HET1[0-31], N2HET2[0], N2HET2[2], N2HET2[4], N2HET2[5], N2HET2[6], N2HET2[7], N2HET2[8], N2HET2[9], N2HET2[10], N2HET2[11], N2HET2[12], N2HET2[13], N2HET2[14], N2HET2[15], N2HET2[16], N2HET2[18], SPI2nCS[0], SPI2nENA, SPI4nCS[0], SPI4nENA |
selectable 8 mA / 2 mA |
ECLK, SPI2CLK, SPI2SIMO, SPI2SOMI The default output buffer drive strength is 8 mA for these signals. |
Signal | Control Bit | Address | 8 mA | 2 mA |
---|---|---|---|---|
ECLK | SYSPC10[0] | 0xFFFF FF78 | 0 | 1 |
SPI2CLK | SPI2PC9[9] | 0xFFF7 F668 | 0 | 1 |
SPI2SIMO | SPI2PC9[10] | 0xFFF7 F668 | 0 | 1 |
SPI2SOMI | SPI2PC9[11](1) | 0xFFF7 F668 | 0 | 1 |
Parameter | MIN | MAX | Unit | |
---|---|---|---|---|
tpw | Input minimum pulse width | tc(VCLK) + 10(2) | ns | |
tin_slew | Time for input signal to go from VIL to VIH or from VIH to VIL | 1 | ns |
Parameter | MIN | MAX | Unit | |||
---|---|---|---|---|---|---|
Rise time, tr | 8 mA low EMI pins (see Table 5-4) |
CL = 15 pF | 2.5 | ns | ||
CL = 50 pF | 4 | |||||
CL = 100 pF | 7.2 | |||||
CL = 150 pF | 12.5 | |||||
Fall time, tf | CL = 15 pF | 2.5 | ns | |||
CL = 50 pF | 4 | |||||
CL = 100 pF | 7.2 | |||||
CL = 150 pF | 12.5 | |||||
Rise time, tr | 4 mA low EMI pins (see Table 5-4) |
CL = 15 pF | 5.6 | ns | ||
CL = 50 pF | 10.4 | |||||
CL = 100 pF | 16.8 | |||||
CL = 150 pF | 23.2 | |||||
Fall time, tf | CL = 15 pF | 5.6 | ns | |||
CL= 50 pF | 10.4 | |||||
CL = 100 pF | 16.8 | |||||
CL = 150 pF | 23.2 | |||||
Rise time, tr | 2 mA-z low EMI pins (see Table 5-4) |
CL = 15 pF | 8 | ns | ||
CL = 50 pF | 15 | |||||
CL = 100 pF | 23 | |||||
CL = 150 pF | 33 | |||||
Fall time, tf | CL = 15 pF | 8 | ns | |||
CL = 50 pF | 15 | |||||
CL = 100 pF | 23 | |||||
CL = 150 pF | 33 | |||||
Rise time, tr | Selectable 8 mA / 2 mA-z pins (see Table 5-4) |
8 mA mode | CL = 15 pF | 2.5 | ns | |
CL = 50 pF | 4 | |||||
CL = 100 pF | 7.2 | |||||
CL = 150 pF | 12.5 | |||||
Fall time, tf | CL = 15 pF | 2.5 | ns | |||
CL = 50 pF | 4 | |||||
CL = 100 pF | 7.2 | |||||
CL = 150 pF | 12.5 | |||||
Rise time, tr | 2 mA-z mode | CL = 15 pF | 8 | ns | ||
CL = 50 pF | 15 | |||||
CL = 100 pF | 23 | |||||
CL = 150 pF | 33 | |||||
Fall time, tf | CL = 15 pF | 8 | ns | |||
CL = 50 pF | 15 | |||||
CL = 100 pF | 23 | |||||
CL = 150 pF | 33 |
Parameter | MIN | MAX | UNIT | |
---|---|---|---|---|
td(parallel_out) | Delay between low to high, or high to low transition of general-purpose output signals that can be configured by an application in parallel, e.g. all signals in a GIOA port, or all N2HET1 signals, etc. | 6 | ns |
The low-EMI output buffer has been designed explicitly to address the issue of decoupling sources of emissions from the pins which they drive. This is accomplished by adaptively controlling the impedance of the output buffer, and is particularly effective with capacitive loads.
This is not the default mode of operation of the low-EMI output buffers and must be enabled by setting the system module GPCR1 register for the desired module or signal, as shown in . The adaptive impedance control circuit monitors the DC bias point of the output signal. The buffer internally generates two reference levels, VREFLOW and VREFHIGH, which are set to approximately 10% and 90% of VCCIO, respectively.
Once the output buffer has driven the output to a low level, if the output voltage is below VREFLOW, then the output buffer’s impedance will increase to hi-Z. A high degree of decoupling between the internal ground bus and the output pin will occur with capacitive loads, or any load in which no current is flowing, e.g. the buffer is driving low on a resistive path to ground. Current loads on the buffer which attempt to pull the output voltage above VREFLOW will be opposed by the buffer’s output impedance so as to maintain the output voltage at or below VREFLOW.
Conversely, once the output buffer has driven the output to a high level, if the output voltage is above VREFHIGH then the output buffer’s impedance will again increase to hi-Z. A high degree of decoupling between internal power bus ad output pin will occur with capacitive loads or any loads in which no current is flowing, e.g. buffer is driving high on a resistive path to VCCIO. Current loads on the buffer which attempt to pull the output voltage below VREFHIGH will be opposed by the buffer’s output impedance so as to maintain the output voltage at or above VREFHIGH.
The bandwidth of the control circuitry is relatively low, so that the output buffer in adaptive impedance control mode cannot respond to high-frequency noise coupling into the buffer’s power buses. In this manner, internal bus noise approaching 20% peak-to-peak of VCCIO can be rejected.
Unlike standard output buffers which clamp to the rails, an output buffer in impedance control mode will allow a positive current load to pull the output voltage up to VCCIO + 0.6V without opposition. Also, a negative current load will pull the output voltage down to VSSIO – 0.6V without opposition. This is not an issue since the actual clamp current capability is always greater than the IOH / IOL specifications.
The low-EMI output buffers are automatically configured to be in the standard buffer mode when the device enters a low-power mode.
Module or Signal Name | Control Register to Enable Low-EMI Mode |
---|---|
Module: MibSPI1 | GPREG1.0 |
Module: SPI2 | GPREG1.1 |
Module: MibSPI3 | GPREG1.2 |
Reserved | GPREG1.3 |
Module: MibSPI5 | GPREG1.4 |
Reserved | GPREG1.5 |
Module: EMIF | GPREG1.6 |
Reserved | GPREG1.7 |
Signal: TMS | GPREG1.8 |
Signal: TDI | GPREG1.9 |
Signal: TDO | GPREG1.10 |
Signal: RTCK | GPREG1.11 |
Signal: TEST | GPREG1.12 |
Signal: nERROR | GPREG1.13 |
Signal: AD1EVT | GPREG1.14 |