SPNS229C October   2014  – November 2016 RM44L520 , RM44L920

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Device Comparison
    1. 3.1 Related Products
  4. 4 Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
      1. 4.1.1 PGE QFP Package Pinout (144-Pin)
      2. 4.1.2 PZ QFP Package Pinout (100-Pin)
    2. 4.2 Signal Descriptions
      1. 4.2.1 PGE Package Terminal Functions
        1. 4.2.1.1  Multibuffered Analog-to-Digital Converters (MibADCs)
        2. 4.2.1.2  Enhanced High-End Timer (N2HET) Modules
        3. 4.2.1.3  Enhanced Capture Modules (eCAP)
        4. 4.2.1.4  Enhanced Quadrature Encoder Pulse Modules (eQEP)
        5. 4.2.1.5  Enhanced Pulse-Width Modulator Modules (ePWM)
        6. 4.2.1.6  General-Purpose Input/Output (GIO)
        7. 4.2.1.7  Controller Area Network Controllers (DCAN)
        8. 4.2.1.8  Local Interconnect Network Interface Module (LIN)
        9. 4.2.1.9  Standard Serial Communication Interface (SCI)
        10. 4.2.1.10 Inter-Integrated Circuit Interface Module (I2C)
        11. 4.2.1.11 Standard Serial Peripheral Interface (SPI)
        12. 4.2.1.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)
        13. 4.2.1.13 System Module Interface
        14. 4.2.1.14 Clock Inputs and Outputs
        15. 4.2.1.15 Test and Debug Modules Interface
        16. 4.2.1.16 Flash Supply and Test Pads
        17. 4.2.1.17 Supply for Core Logic: 1.2V nominal
        18. 4.2.1.18 Supply for I/O Cells: 3.3V nominal
        19. 4.2.1.19 Ground Reference for All Supplies Except VCCAD
      2. 4.2.2 PZ Package Terminal Functions
        1. 4.2.2.1  High-End Timer (N2HET) Modules
        2. 4.2.2.2  Enhanced Capture Modules (eCAP)
        3. 4.2.2.3  Enhanced Quadrature Encoder Pulse Modules (eQEP)
        4. 4.2.2.4  Enhanced Pulse-Width Modulator Modules (ePWM)
        5. 4.2.2.5  General-Purpose Input/Output (GIO)
        6. 4.2.2.6  Controller Area Network Interface Modules (DCAN1, DCAN2)
        7. 4.2.2.7  Standard Serial Peripheral Interfaces (SPI2 and SPI4)
        8. 4.2.2.8  Multibuffered Serial Peripheral Interface (MibSPI1 and MibSPI3)
        9. 4.2.2.9  Local Interconnect Network Controller (LIN)
        10. 4.2.2.10 Multibuffered Analog-to-Digital Converter (MibADC)
        11. 4.2.2.11 System Module Interface
        12. 4.2.2.12 Clock Inputs and Outputs
        13. 4.2.2.13 Test and Debug Modules Interface
        14. 4.2.2.14 Flash Supply and Test Pads
        15. 4.2.2.15 Supply for Core Logic: 1.2-V Nominal
        16. 4.2.2.16 Supply for I/O Cells: 3.3-V Nominal
        17. 4.2.2.17 Ground Reference for All Supplies Except VCCAD
    3. 4.3 Pin Multiplexing
      1. 4.3.1 Output Multiplexing
      2. 4.3.2 Multiplexing of Inputs
    4. 4.4 Buffer Type
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power-On Hours (POH)
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Input/Output Electrical Characteristics Over Recommended Operating Conditions
    6. 5.6 Power Consumption Over Recommended Operating Conditions
    7. 5.7 Thermal Resistance Characteristics
    8. 5.8 Timing and Switching Characteristics
      1. 5.8.1 SYSCLK (Frequencies)
        1. 5.8.1.1 Switching Characteristics over Recommended Operating Conditions for Clock Domains
        2. 5.8.1.2 Wait States Required - PGE and PZ Packages
  6. 6 System Information and Electrical Specifications
    1. 6.1  Device Power Domains
    2. 6.2  Voltage Monitor Characteristics
      1. 6.2.1 Important Considerations
      2. 6.2.2 Voltage Monitor Operation
      3. 6.2.3 Supply Filtering
    3. 6.3  Power Sequencing and Power-On Reset
      1. 6.3.1 Power-Up Sequence
      2. 6.3.2 Power-Down Sequence
      3. 6.3.3 Power-On Reset: nPORRST
        1. 6.3.3.1 nPORRST Electrical and Timing Requirements
    4. 6.4  Warm Reset (nRST)
      1. 6.4.1 Causes of Warm Reset
      2. 6.4.2 nRST Timing Requirements
    5. 6.5  ARM Cortex-R4F CPU Information
      1. 6.5.1 Summary of ARM Cortex-R4F CPU Features
      2. 6.5.2 ARM Cortex-R4F CPU Features Enabled by Software
      3. 6.5.3 Dual Core Implementation
      4. 6.5.4 Duplicate Clock Tree After GCLK
      5. 6.5.5 ARM Cortex-R4F CPU Compare Module (CCM) for Safety
      6. 6.5.6 CPU Self-Test
        1. 6.5.6.1 Application Sequence for CPU Self-Test
        2. 6.5.6.2 CPU Self-Test Clock Configuration
        3. 6.5.6.3 CPU Self-Test Coverage
    6. 6.6  Clocks
      1. 6.6.1 Clock Sources
        1. 6.6.1.1 Main Oscillator
          1. 6.6.1.1.1 Timing Requirements for Main Oscillator
        2. 6.6.1.2 Low-Power Oscillator
          1. 6.6.1.2.1 Features
          2. 6.6.1.2.2 LPO Electrical and Timing Specifications
        3. 6.6.1.3 Phase-Locked Loop (PLL) Clock Module
          1. 6.6.1.3.1 Block Diagram
          2. 6.6.1.3.2 PLL Timing Specifications
        4. 6.6.1.4 External Clock Inputs
      2. 6.6.2 Clock Domains
        1. 6.6.2.1 Clock Domain Descriptions
        2. 6.6.2.2 Mapping of Clock Domains to Device Modules
      3. 6.6.3 Clock Test Mode
    7. 6.7  Clock Monitoring
      1. 6.7.1 Clock Monitor Timings
      2. 6.7.2 External Clock (ECLK) Output Functionality
      3. 6.7.3 Dual Clock Comparators
        1. 6.7.3.1 Features
        2. 6.7.3.2 Mapping of DCC Clock Source Inputs
    8. 6.8  Glitch Filters
    9. 6.9  Device Memory Map
      1. 6.9.1 Memory Map Diagram
      2. 6.9.2 Memory Map Table
      3. 6.9.3 Special Consideration for CPU Access Errors Resulting in Imprecise Aborts
      4. 6.9.4 Master/Slave Access Privileges
      5. 6.9.5 Special Notes on Accesses to Certain Slaves
    10. 6.10 Flash Memory
      1. 6.10.1 Flash Memory Configuration
      2. 6.10.2 Main Features of Flash Module
      3. 6.10.3 ECC Protection for Flash Accesses
      4. 6.10.4 Flash Access Speeds
      5. 6.10.5 Program Flash
      6. 6.10.6 Data Flash
    11. 6.11 Tightly Coupled RAM Interface Module
      1. 6.11.1 Features
      2. 6.11.2 TCRAMW ECC Support
    12. 6.12 Parity Protection for Accesses to Peripheral RAMs
    13. 6.13 On-Chip SRAM Initialization and Testing
      1. 6.13.1 On-Chip SRAM Self-Test Using PBIST
        1. 6.13.1.1 Features
        2. 6.13.1.2 PBIST RAM Groups
      2. 6.13.2 On-Chip SRAM Auto Initialization
    14. 6.14 Vectored Interrupt Manager
      1. 6.14.1 VIM Features
      2. 6.14.2 Interrupt Request Assignments
    15. 6.15 DMA Controller
      1. 6.15.1 DMA Features
      2. 6.15.2 Default DMA Request Map
    16. 6.16 Real-Time Interrupt Module
      1. 6.16.1 Features
      2. 6.16.2 Block Diagrams
      3. 6.16.3 Clock Source Options
      4. 6.16.4 Network Time Synchronization Inputs
    17. 6.17 Error Signaling Module
      1. 6.17.1 ESM Features
      2. 6.17.2 ESM Channel Assignments
    18. 6.18 Reset/Abort/Error Sources
    19. 6.19 Digital Windowed Watchdog
    20. 6.20 Debug Subsystem
      1. 6.20.1 Block Diagram
      2. 6.20.2 Debug Components Memory Map
      3. 6.20.3 JTAG Identification Code
      4. 6.20.4 Debug ROM
      5. 6.20.5 JTAG Scan Interface Timings
      6. 6.20.6 Advanced JTAG Security Module
      7. 6.20.7 Boundary Scan Chain
  7. 7 Peripheral Information and Electrical Specifications
    1. 7.1  I/O Timings
      1. 7.1.1 Input Timings
      2. 7.1.2 Output Timings
        1. 7.1.2.1 Low-EMI Output Buffers
    2. 7.2  Enhanced PWM Modules (ePWM)
      1. 7.2.1 ePWM Clocking and Reset
      2. 7.2.2 Synchronization of ePWMx Time-Base Counters
      3. 7.2.3 Synchronizing all ePWM Modules to the N2HET1 Module Time Base
      4. 7.2.4 Phase-Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 7.2.5 ePWM Synchronization with External Devices
      6. 7.2.6 ePWM Trip Zones
        1. 7.2.6.1 Trip Zones TZ1n, TZ2n, TZ3n
        2. 7.2.6.2 Trip Zone TZ4n
        3. 7.2.6.3 Trip Zone TZ5n
        4. 7.2.6.4 Trip Zone TZ6n
      7. 7.2.7 Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs
      8. 7.2.8 Enhanced Translator-Pulse Width Modulator (ePWMx) Timings
    3. 7.3  Enhanced Capture Modules (eCAP)
      1. 7.3.1 Clock Enable Control for eCAPx Modules
      2. 7.3.2 PWM Output Capability of eCAPx
      3. 7.3.3 Input Connection to eCAPx Modules
      4. 7.3.4 Enhanced Capture Module (eCAP) Electrical Data/Timing
    4. 7.4  Enhanced Quadrature Encoder (eQEP)
      1. 7.4.1 Clock Enable Control for eQEPx Modules
      2. 7.4.2 Using eQEPx Phase Error to Trip ePWMx Outputs
      3. 7.4.3 Input Connections to eQEPx Modules
      4. 7.4.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing
    5. 7.5  12-Bit Multibuffered Analog-to-Digital Converter (MibADC)
      1. 7.5.1 Features
      2. 7.5.2 Event Trigger Options
        1. 7.5.2.1 MibADC1 Event Trigger Hookup
        2. 7.5.2.2 MibADC2 Event Trigger Hookup
        3. 7.5.2.3 Controlling ADC1 and ADC2 Event Trigger Options Using SOC Output from ePWM Modules
      3. 7.5.3 ADC Electrical and Timing Specifications
      4. 7.5.4 Performance (Accuracy) Specifications
        1. 7.5.4.1 MibADC Nonlinearity Errors
        2. 7.5.4.2 MibADC Total Error
    6. 7.6  General-Purpose Input/Output
      1. 7.6.1 Features
    7. 7.7  Enhanced High-End Timer (N2HET)
      1. 7.7.1 Features
      2. 7.7.2 N2HET RAM Organization
      3. 7.7.3 Input Timing Specifications
      4. 7.7.4 N2HET1 to N2HET2 Synchronization
      5. 7.7.5 N2HET Checking
        1. 7.7.5.1 Internal Monitoring
        2. 7.7.5.2 Output Monitoring Using Dual Clock Comparator (DCC)
      6. 7.7.6 Disabling N2HET Outputs
      7. 7.7.7 High-End Timer Transfer Unit (HET)
        1. 7.7.7.1 Features
        2. 7.7.7.2 Trigger Connections
    8. 7.8  Controller Area Network (DCAN)
      1. 7.8.1 Features
      2. 7.8.2 Electrical and Timing Specifications
    9. 7.9  Local Interconnect Network Interface (LIN)
      1. 7.9.1 LIN Features
    10. 7.10 Serial Communication Interface (SCI)
      1. 7.10.1 Features
    11. 7.11 Inter-Integrated Circuit (I2C) Module
      1. 7.11.1 Features
      2. 7.11.2 I2C I/O Timing Specifications
    12. 7.12 Multibuffered / Standard Serial Peripheral Interface
      1. 7.12.1 Features
      2. 7.12.2 MibSPI Transmit and Receive RAM Organization
      3. 7.12.3 MibSPI Transmit Trigger Events
        1. 7.12.3.1 MibSPI1 Event Trigger Hookup
        2. 7.12.3.2 MibSPI3 Event Trigger Hookup
        3. 7.12.3.3 MibSPI5 Event Trigger Hookup
      4. 7.12.4 MibSPI/SPI Master Mode I/O Timing Specifications
      5. 7.12.5 SPI Slave Mode I/O Timings
  8. 8 Applications, Implementation, and Layout
    1. 8.1 TI Designs or Reference Designs
  9. 9 Device and Documentation Support
    1. 9.1  Getting Started and Next Steps
    2. 9.2  Device and Development-Support Tool Nomenclature
    3. 9.3  Tools and Software
      1. 9.3.1 Kits and Evaluation Modules for Hercules RM MCUs
      2. 9.3.2 Development Tools
      3. 9.3.3 Software
    4. 9.4  Documentation Support
    5. 9.5  Related Links
    6. 9.6  Community Resources
    7. 9.7  Trademarks
    8. 9.8  Electrostatic Discharge Caution
    9. 9.9  Glossary
    10. 9.10 Device Identification
      1. 9.10.1 Device Identification Code Register
      2. 9.10.2 Die Identification Registers
    11. 9.11 Module Certifications
      1. 9.11.1 DCAN Certification
      2. 9.11.2 LIN Certification
        1. 9.11.2.1 LIN Master Mode
        2. 9.11.2.2 LIN Slave Mode - Fixed Baud Rate
        3. 9.11.2.3 LIN Slave Mode - Adaptive Baud Rate
  10. 10Mechanical Packaging and Orderable Information
    1. 10.1 Packaging Information

4 Terminal Configuration and Functions

4.1 Pin Diagrams

4.1.1 PGE QFP Package Pinout (144-Pin)

RM44L920 RM44L520 PGE_144B_spns225.gif
A. Pins can have multiplexed functions. Only the default function is shown in Figure 4-1.
Figure 4-1 PGE QFP Package Pinout (144-Pin)

4.1.2 PZ QFP Package Pinout (100-Pin)

RM44L920 RM44L520 pzA_100_pin_f3.gif Figure 4-2 PZ QFP Package Pinout (100-Pin)

4.2 Signal Descriptions

The signal descriptions section shows pin information in module function order per package.

Section 4.2.1 and Section 4.2.2 identify the external signal names, the associated pin or ball numbers along with the mechanical package designator, the pin or ball type (Input, Output, I/O, Power, or Ground), whether the pin or ball has any internal pullup/pulldown, whether the pin or ball can be configured as a GIO, and a functional pin or ball description. The first signal name listed is the primary function for that terminal (pin or ball). The signal name in Bold is the function being described. For information on how to select between different multiplexed functions, see Section 4.3, Pin Multiplexing or see the I/O Multiplexing and Control Module (IOMM) chapter of the RM44Lx 16/32-Bit RISC Flash Microcontroller Technical Reference Manual (SPNU608).

NOTE

All I/O signals except nRST are configured as inputs while nPORRST is low and immediately after nPORRST goes high.


All output-only signals are configured as high impedance while nPORRST is low, and are configured as outputs immediately after nPORRST goes high.


While nPORRST is low, the input buffers are disabled, and the output buffers are high impedance.


In the Terminal Functions tables of Section 4.2.1 and Section 4.2.2, the RESET PULL STATE is the state of the pullup or pulldown while nPORRST is low and immediately after nPORRST goes high. The default pull direction may change when software configures the pin for an alternate function. The PULL TYPE is the type of pull asserted when the signal name in bold is enabled for the given terminal.

4.2.1 PGE Package Terminal Functions

4.2.1.1 Multibuffered Analog-to-Digital Converters (MibADCs)

Table 4-1 PGE Multibuffered Analog-to-Digital Converters (MibADC1, MibADC2)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
ADREFHI(1) 66 Power – None ADC high reference supply
ADREFLO(1) 67 Power ADC low reference supply
VCCAD(1) 69 Power Operating supply for ADC
VSSAD(1) 68 Ground
AD1EVT 86 I/O Pulldown Programmable, 20 µA ADC1 event trigger input, or GIO
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/
EQEP1I/N2HET2_PIN_nDIS		 55 I/O Pullup Programmable, 20 µA ADC2 event trigger input, or GIO
AD1IN[0] 60 Input – None ADC1 analog input
AD1IN[01] 71
AD1IN[02] 73
AD1IN[03] 74
AD1IN[04] 76
AD1IN[05] 78
AD1IN[06] 80
AD1IN[07] 61
AD1IN[08] / AD2IN[08] 83 Input – None ADC1/ADC2 shared analog inputs
AD1IN[09] / AD2IN[09] 70
AD1IN[10] / AD2IN[10] 72
AD1IN[11] / AD2IN[11] 75
AD1IN[12] / AD2IN[12] 77
AD1IN[13] / AD2IN[13] 79
AD1IN[14] / AD2IN[14] 82
AD1IN[15] / AD2IN[15] 85
AD1IN[16] / AD2IN[0] 58
AD1IN[17] / AD2IN[01] 59
AD1IN[18] / AD2IN[02] 62
AD1IN[19] / AD2IN[03] 63
AD1IN[20] / AD2IN[04] 64
AD1IN[21] / AD2IN[05] 65
AD1IN[22] / AD2IN[06] 81
AD1IN[23] / AD2IN[07] 84
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2 51 Output Pullup – AWM1 external analog mux enable
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3 52 Output Pullup – AWM1 external analog mux select line0
MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A 53 Output Pullup – AWM1 external analog mux select line0
(1) The ADREFHI, ADREFLO, VCCAD and VSSAD connections are common for both ADC cores.

4.2.1.2 Enhanced High-End Timer (N2HET) Modules

Table 4-2 PGE Enhanced High-End Timer (N2HET) Modules

TERMINAL SIGNAL TYPE RESET
PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 144 PGE
N2HET1[0]/SPI4CLK/EPWM2B 25 I/O Pulldown Programmable, 20 µA

N2HET1 timer input capture or output compare, or GIO.

Each terminal has a suppression filter with a programmable duration.
N2HET1[01]/SPI4NENA/N2HET2[8]/EQEP2A 23
N2HET1[02]/SPI4SIMO[0]/EPWM3A 30
N2HET1[03]/SPI4NCS[0]/N2HET2[10]/EQEP2B 24
N2HET1[04]/EPWM4B 36
N2HET1[05]/SPI4SOMI[0]/N2HET2[12]/EPWM3B 31
N2HET1[06]/SCIRX/EPWM5A 38
N2HET1[07]/N2HET2[14]/EPWM7B 33
N2HET1[08]/MIBSPI1SIMO[1]/ 106
N2HET1[09]/N2HET2[16]/EPWM7A 35
N2HET1[10]/nTZ3 118
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO 6
N2HET1[12] 124
N2HET1[13]/SCITX/EPWM5B 39
N2HET1[14] 125
N2HET1[15]/MIBSPI1NCS[4]/ECAP1 41
N2HET1[16]/EPWM1SYNCI/EPWM1SYNCO 139
MIBSPI1NCS[1]/N2HET1[17]/EQEP1S 130 Pullup
N2HET1[18]/EPWM6A 140 Pulldown
MIBSPI1NCS[2]/N2HET1[19] 40 Pullup
N2HET1[20]/EPWM6B 141 Pulldown
N2HET1[22] 15
MIBSPI1NENA/N2HET1[23]/ECAP4 96 Pullup
N2HET1[24]/MIBSPI1NCS[5] 91 Pulldown
MIBSPI3NCS[1]/N2HET1[25] 37 Pullup
N2HET1[26] 92 Pulldown
MIBSPI3NCS[2]/I2CSDA/N2HET1[27]/nTZ2 4 Pullup
N2HET1[28] 107 Pulldown
MIBSPI3NCS[3]/I2CSCL/N2HET1[29]/nTZ1 3 Pullup
N2HET1[30]/EQEP2S 127 Pulldown
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B 54 Pullup
GIOA[5]/EXTCLKIN1/EPWM1A/N2HET1_PIN_nDIS 14 Pulldown Disable selected PWM outputs
GIOA[2]/N2HET2[0]/EQEP2I 9 I/O Pulldown Programmable, 20 µA

N2HET2 timer input capture or output compare, or GIO

Each terminal has a suppression filter with a programmable duration.
GIOA[6]/N2HET2[4]/EPWM1B 16
GIOA[7]/N2HET2[6]EPWM2A 22
N2HET1[01]/SPI4NENA//N2HET2[8] 23
N2HET1[03]/SPI4NCS[0]/N2HET2[10]/EQEP2B 24
N2HET1[05]/SPI4SOMI[0]/N2HET2[12]/EQEP3B 31
N2HET1[07]/N2HET2[14]/EPWM7B 33
N2HET1[09]/N2HET2[16] 35
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO 6
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1l/N2HET2_PIN_nDIS 55 Pullup Disable selected PWM outputs

4.2.1.3 Enhanced Capture Modules (eCAP)

Table 4-3 PGE Enhanced Capture Modules (eCAP)(1)

TERMINAL SIGNAL TYPE RESET
PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 144 PGE
N2HET1[15]/MIBSPI1NCS[4]/ECAP1 41 I/O Pulldown Fixed, 20 µA Enhanced Capture Module 1 I/O
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2 51 Pullup Enhanced Capture Module 2 I/O
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3 52 Enhanced Capture Module 3 I/O
MIBSPI1NENA/N2HET1[23]/ECAP4 96 Enhanced Capture Module 4 I/O
MIBSPI5NENA/MIBSPI5SOMI[1]/ECAP5 97 Enhanced Capture Module 5 I/O
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/ECAP6 105 Enhanced Capture Module 6 I/O
(1) These signals, when used as inputs, are double-synchronized and then optionally filtered with a 6-cycle VCLK4-based counter.

4.2.1.4 Enhanced Quadrature Encoder Pulse Modules (eQEP)

Table 4-4 PGE Enhanced Quadrature Encoder Pulse Modules (eQEP)(1)

TERMINAL SIGNAL TYPE RESET PULL STATE PULL TYPE DESCRIPTION
SIGNAL NAME 144 PGE
MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A 53 Input Pullup Fixed, 20 µA Enhanced QEP1 Input A
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B 54 Input Enhanced QEP1 Input B
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1I/N2HET2_PIN_nDIS 55 I/O Enhanced QEP1 Index
MIBSPI1NCS[1]/N2HET1[17]//EQEP1S 130 I/O Enhanced QEP1 Strobe
N2HET1[01]/SPI4NENA/N2HET2[8]/EQEP2A 23 Input Pulldown Enhanced QEP2 Input A
N2HET1[03]/SPI4NCS[0]/N2HET2[10]/EQEP2B 24 Input Enhanced QEP2 Input B
GIOA[2]/N2HET2[0]/EQEP2I 9 I/O Enhanced QEP2 Index
N2HET1[30]/EQEP2S 127 I/O Enhanced QEP2 Strobe
(1) These signals are double-synchronized and then optionally filtered with a 6-cycle VCLK4-based counter.

4.2.1.5 Enhanced Pulse-Width Modulator Modules (ePWM)

Table 4-5 PGE Enhanced Pulse-Width Modulator Modules (ePWM)

TERMINAL SIGNAL TYPE RESET
PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 144 PGE
GIOA[5]/EXTCLKIN1/EPWM1A/N2HET1_PIN_nDIS 14 Output Pulldown – Enhanced PWM1 Output A
GIOA[6]/N2HET2[4]/EPWM1B 16 Enhanced PWM1 Output B
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO 6 External ePWM Sync Pulse Output
N2HET1[16]/EPWM1SYNCI/EPWM1SYNCO 139 Input Pullup Fixed, 20 µA External ePWM Sync Pulse Output
GIOA[7]/N2HET2[6]/EPWM2A 22 Output Pulldown – Enhanced PWM2 Output A
N2HET1[0]/SPI4CLK/EPWM2B 25 Enhanced PWM2 Output B
N2HET1[02]/SPI4SIMO[0]/EPWM3A 30 Enhanced PWM3 Output A
N2HET1[05]/SPI4SOMI[0]/N2HET2[12]/EPWM3B 31 Enhanced PWM3 Output B
MIBSPI5NCS[0]/EPWM4A 32 Output Pullup – Enhanced PWM4 Output A
N2HET1[04]/EPWM4B 36 Output Pulldown – Enhanced PWM4 Output B
N2HET1[06]/SCIRX/EPWM5A 38 Enhanced PWM5 Output A
N2HET1[13]/SCITX/EPWM5B 39 Enhanced PWM5 Output B
N2HET1[18]/EPWM6A 140 Enhanced PWM6 Output A
N2HET1[20]/EPWM6B 141 Enhanced PWM6 Output B
N2HET1[09]/N2HET2[16]/EPWM7A 35 Enhanced PWM7 Output A
N2HET1[07]/N2HET2[14]/EPWM7B 33 Enhanced PWM7 Output B
MIBSPI3NCS[3]/I2CSCL/N2HET1[29]/nTZ1 3 Input Pullup Fixed, 20 µA Trip Zone Inputs 1, 2 and 3. These signals are either connected asynchronously to the ePWMx trip zone inputs, or double-synchronized with VCLK4, or double-synchronized and then filtered with a 6-cycle VCLK4-based counter before connecting to the ePWMx trip zone inputs.
MIBSPI3NCS[2]/I2CSDA/N2HET1[27]/nTZ2 4
N2HET1[10]/nTZ3 118 Pulldown

4.2.1.6 General-Purpose Input/Output (GIO)

Table 4-6 PGE General-Purpose Input/Output (GIO)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
GIOA[0] 2 I/O Pulldown Programmable, 20 µA General-purpose I/O.
All GIO terminals are capable of generating interrupts to the CPU on rising / falling / both edges.
GIOA[1] 5
GIOA[2]/N2HET2[0]/EQEPII 9
GIOA[5]/EXTCLKIN1/EPWM1A/N2HET1_PIN_nDIS 14
GIOA[6]/N2HET2[4]/EPWM1B 16
GIOA[7]/N2HET2[6]/EPWM2A 22
GIOB[0] 126
GIOB[1] 133
GIOB[2] 142
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1I/N2HET2_PIN_nDIS 55(1) Pullup
GIOB[3] 1 Pulldown
(1) GIOB[2] cannot output a level on to pin 55. Only the input functionality is supported so that the application can generate an interrupt whenever the N2HET2_PIN_nDIS is asserted (driven low). Also, a pullup is enabled on the input. This is not programmable using the GIO module control registers.

4.2.1.7 Controller Area Network Controllers (DCAN)

Table 4-7 PGE Controller Area Network Controllers (DCAN)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
CAN1RX 90 I/O Pullup Programmable,  20 µA CAN1 receive, or GIO
CAN1TX 89 CAN1 transmit, or GIO
CAN2RX 129 CAN2 receive, or GIO
CAN2TX 128 CAN2 transmit, or GIO
CAN3RX 12 CAN3 receive, or GIO
CAN3TX 13 CAN3 transmit, or GIO

4.2.1.8 Local Interconnect Network Interface Module (LIN)

Table 4-8 PGE Local Interconnect Network Interface Module (LIN)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
LINRX 131 I/O Pullup Programmable,  20 µA LIN receive, or GIO
LINTX 132 LIN transmit, or GIO

4.2.1.9 Standard Serial Communication Interface (SCI)

Table 4-9 PGE Standard Serial Communication Interface (SCI)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
N2HET1[06]/SCIRX/EPWM5A 38 I/O Pulldown Programmable, 20 µA SCI receive, or GIO
N2HET1[13]/SCITX/EPWM5B 39 SCI transmit, or GIO

4.2.1.10 Inter-Integrated Circuit Interface Module (I2C)

Table 4-10 PGE Inter-Integrated Circuit Interface Module (I2C)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
MIBSPI3NCS[2]/I2CSDA/N2HET1[27]/nTZ2 4 I/O Pullup Programmable, 20 µA I2C serial data, or GIO
MIBSPI3NCS[3]/I2CSCL/N2HET1[29]/nTZ1 3 I2C serial clock, or GIO

4.2.1.11 Standard Serial Peripheral Interface (SPI)

Table 4-11 PGE Standard Serial Peripheral Interface (SPI)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
N2HET1[0]/SPI4CLK/EPWM2B 25 I/O Pulldown Programmable, 20 µA SPI4 clock, or GIO
N2HET1[03]/SPI4NCS[0]/N2HET2[10]/EQEP2B 24 SPI4 chip select, or GIO
N2HET1[01]/SPI4NENA/N2HET2[8]/EQEP2A 23 SPI4 enable, or GIO
N2HET1[02]/SPI4SIMO[0]/EPWM3A 30 SPI4 slave-input master-output, or GIO
N2HET1[05]/SPI4SOMI[0]/N2HET2[12]/EPWM3B 31 SPI4 slave-output master-input, or GIO

4.2.1.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)

Table 4-12 PGE Multibuffered Serial Peripheral Interface Modules (MibSPI)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
MIBSPI1CLK 95 I/O Pullup Programmable, 20 µA MibSPI1 clock, or GIO
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/ECAP6 105 MibSPI1 chip select, or GIO
MIBSPI1NCS[1]/N2HET1[17]//EQEP1S 130
MIBSPI1NCS[2]/N2HET1[19]/ 40
N2HET1[15]/MIBSPI1NCS[4]/ECAP1 41 Pulldown Programmable, 20 µA MibSPI1 chip select, or GIO
N2HET1[24]/MIBSPI1NCS[5] 91
MIBSPI1NENA/N2HET1[23]/ECAP4 96 Pullup Programmable, 20 µA MibSPI1 enable, or GIO
MIBSPI1SIMO[0] 93 MibSPI1 slave-in master-out, or GIO
N2HET1[08]/MIBSPI1SIMO[1] 106 Pulldown Programmable, 20 µA MibSPI1 slave-in master-out, or GIO
MIBSPI1SOMI[0] 94 Pullup Programmable, 20 µA MibSPI1 slave-out master-in, or GIO
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/ECAP6 105
MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A 53 I/O Pullup Programmable, 20 µA MibSPI3 clock, or GIO
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1I/N2HET2_PIN_nDIS 55 MibSPI3 chip select, or GIO
MIBSPI3NCS[1]/N2HET1[25] 37
MIBSPI3NCS[2]/I2CSDA/N2HET1[27]/nTZ2 4
MIBSPI3NCS[3]/I2CSCL/N2HET1[29]/nTZ1 3
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO 6 Pulldown Programmable, 20 µA MibSPI3 chip select, or GIO
MIBSPI3NENA /MIBSPI3NCS[5]/N2HET1[31]/EQEP1B 54 Pullup Programmable, 20 µA MibSPI3 chip select, or GIO
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B 54 MibSPI3 enable, or GIO
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3 52 MibSPI3 slave-in master-out, or GIO
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2 51 MibSPI3 slave-out master-in, or GIO
MIBSPI5CLK 100 I/O Pullup Programmable, 20 µA MibSPI5 clock, or GIO
MIBSPI5NCS[0]/EPWM4A 32 MibSPI5 chip select, or GIO
MIBSPI5NENA/MIBSPI5SOMI[1]/ECAP5 97 MibSPI5 enable, or GIO
MIBSPI5SIMO[0]/MIBSPI5SOMI[2] 99 MibSPI5 slave-in master-out, or GIO
MIBSPI5SOMI[0] 98 MibSPI5 slave-out master-in, or GIO
MIBSPI5NENA/MIBSPI5SOMI[1]/ECAP5 97 MibSPI5 SOMI[0], or GIO
MIBSPI5SIMO[0]/MIBSPI5SOMI[2] 99 MibSPI5 SOMI[0], or GIO

4.2.1.13 System Module Interface

Table 4-13 PGE System Module Interface

TERMINAL SIGNAL TYPE RESET
PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 144 PGE
nPORRST 46 Input Pulldown 100 µA Power-on reset, cold reset
External power supply monitor circuitry must drive nPORRST low when any of the supplies to the microcontroller fall out of the specified range. This terminal has a glitch filter.
See Section 6.8.
nRST 116 I/O Pullup 100 µA System reset, warm reset, bidirectional.
The internal circuitry indicates any reset condition by driving nRST low.
The external circuitry can assert a system reset by driving nRST low. To ensure that an external reset is not arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal.
This terminal has a glitch filter. See Section 6.8.
nERROR 117 I/O Pulldown 20 µA ESM Error Signal
Indicates error of high severity. See Section 6.8.

4.2.1.14 Clock Inputs and Outputs

Table 4-14 PGE Clock Inputs and Outputs

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
OSCIN 18 Input – None From external crystal/resonator, or external clock input
KELVIN_GND 19 Input Kelvin ground for oscillator
OSCOUT 20 Output To external crystal/resonator
ECLK 119 I/O Pulldown Programmable, 20 µA External prescaled clock output, or GIO.
GIOA[5]/EXTCLKIN1/EPWM1A /N2HET1_PIN_nDIS 14 Input Pulldown 20 µA External clock input #1

4.2.1.15 Test and Debug Modules Interface

Table 4-15 PGE Test and Debug Modules Interface

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
TEST 34 Input Pulldown Fixed, 100 µA Test enable. This terminal must be connected to ground directly or via a pulldown resistor.
nTRST 109 Input JTAG test hardware reset
RTCK 113 Output - None JTAG return test clock
TCK 112 Input Pulldown Fixed, 100 µA JTAG test clock
TDI 110 Input Pullup JTAG test data in
TDO 111 Output Pulldown JTAG test data out
TMS 108 Input Pullup JTAG test select

4.2.1.16 Flash Supply and Test Pads

Table 4-16 PGE Flash Supply and Test Pads

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
VCCP 134 3.3-V Power – None Flash pump supply
FLTP1 7 – – None Flash test pads. These terminals are reserved for TI use only. For proper operation these terminals must connect only to a test pad or not be connected at all [no connect (NC)].
FLTP2 8

4.2.1.17 Supply for Core Logic: 1.2V nominal

Table 4-17 PGE Supply for Core Logic: 1.2V nominal

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
VCC 17 1.2-V Power – None Core supply
VCC 29
VCC 45
VCC 48
VCC 49
VCC 57
VCC 87
VCC 101
VCC 114
VCC 123
VCC 137
VCC 143

4.2.1.18 Supply for I/O Cells: 3.3V nominal

Table 4-18 PGE Supply for I/O Cells: 3.3V nominal

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
VCCIO 10 3.3-V Power – None Operating supply for I/Os
VCCIO 26
VCCIO 42
VCCIO 104
VCCIO 120
VCCIO 136

4.2.1.19 Ground Reference for All Supplies Except VCCAD

Table 4-19 PGE Ground Reference for All Supplies Except VCCAD

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
VSS 11 Ground – None Ground reference
VSS 21
VSS 27
VSS 28
VSS 43
VSS 44
VSS 47
VSS 50
VSS 56
VSS 88
VSS 102
VSS 103
VSS 115
VSS 121
VSS 122
VSS 135
VSS 138
VSS 144

4.2.2 PZ Package Terminal Functions

4.2.2.1 High-End Timer (N2HET) Modules

Table 4-20 PZ Enhanced High-End Timer (N2HET) Modules

TERMINAL SIGNAL TYPE RESET PULL STATE PULL TYPE DESCRIPTION
SIGNAL NAME 100 PZ
N2HET1[0]/ SPI4CLK / EPWM2B 19 I/O Pulldown Programmable, 20 µA

N2HET2 timer input capture or output compare, or GIO.

Each terminal has a suppression filter with a programmable duration.

Timer input capture or output compare. The N2HET applicable terminals can be programmed as general-purpose input/output (GIO).
N2HET1[2] / SPI4SIMO / EPWM3A 22
N2HET1[4] / EPWM4B 25
N2HET1[6] / SCIRX / EPWM5A 26
N2HET1[8] / MIBSPI1SIMO[1] 74
N2HET1[10] / nTZ3 83
N2HET1[12] 89
N2HET1[14] 90
N2HET1[16] / EPWM1SYNCI / EPWM1SYNCO 97
MIBSPI1nCS[1] / N2HET1[17] / EQEP1S 93 Pullup
N2HET1[18] / EPWM6A 98 Pulldown
MIBSPI1nCS[2] / N2HET1[19] 27 Pullup
MIBSPI1nCS[3] / N2HET1[21] 39
N2HET1[22] 11 Pulldown
MIBSPI1nENA / N2HET1[23] / ECAP4 68 Pullup
N2HET1[24] / MIBSPI1nCS[5] 64 Pulldown
MIBSPI3nENA / MIBSPI3nCS[5] / N2HET1[31] / EQEP1B 37 Pullup
GIOA[5] / INT[5] / EXTCLKIN /EPWM1A/N2HET1_PIN_nDIS 10 Pulldown Disable selected PWM outputs
GIOA[2] / INT[2] / N2HET2[0] / EQEP2I 5 Pulldown

N2HET2 timer input capture or output compare, or GIO.

Each terminal has a suppression filter with a programmable duration.

Timer input capture or output compare. The N2HET applicable terminals can be programmed as general-purpose input/output (GIO).
GIOA[3] / INT[3] / N2HET2[2] 8
GIOA[6] / INT[6] / N2HET2[4] / EPWM1B 12
GIOA[7] / INT[7] / N2HET2[6] / EPWM2A 18

4.2.2.2 Enhanced Capture Modules (eCAP)

Table 4-21 PZ Enhanced Capture Modules (eCAP)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 100 PZ
MIBSPI3SOMI[0] / AWM1_EXT_ENA / ECAP2 34 I/O Pullup Fixed, 20 µA Enhanced Capture Module 2 I/O
MIBSPI3SIMO[0] / AWM1_EXT_SEL[0] / ECAP3 35 Enhanced Capture Module 3 I/O
MIBSPI1NENA / N2HET1[23] / ECAP4 68 Enhanced Capture Module 4 I/O
MIBSPI1NCS[0] / MIBSPI1SOMI[1] / ECAP6 73 Enhanced Capture Module 6 I/O

4.2.2.3 Enhanced Quadrature Encoder Pulse Modules (eQEP)

Table 4-22 PZ Enhanced Quadrature Encoder Pulse Modules (eQEP)

TERMINAL SIGNAL TYPE RESET PULL STATE PULL TYPE DESCRIPTION
SIGNAL NAME 100 PZ
MIBSPI3CLK / AWM1_EXT_SEL[1] / EQEP1A 36 I/O Pullup Fixed, 20 µA Enhanced QEP1 Input A
MIBSPI3nENA / MIBSPI3nCS[5] / N2HET1[31] / EQEP1B 37 Enhanced QEP1 Input B
MIBSPI3nCS[0] / AD2EVT / GIOB[2] / EQEP1I/N2HET2_PIN_nDIS 38 Enhanced QEP1 Index
MIBSPI1nCS[1] / N2HET1[17] / EQEP1S 93 Enhanced QEP1 Strobe
GIOA[2] / INT[2] / N2HET2[0] / EQEP2I 5 Pulldown Enhanced QEP2 Index

4.2.2.4 Enhanced Pulse-Width Modulator Modules (ePWM)

Table 4-23 PZ Enhanced Pulse-Width Modulator Modules (ePWM)

TERMINAL SIGNAL TYPE RESET PULL STATE PULL TYPE DESCRIPTION
SIGNAL NAME 100 PZ
GIOA[5] / INT[5] / EXTCLKIN / EPWM1A/N2HET1_PIN_nDIS 10 Output Pulldown – Enhanced PWM1 Output A
GIOA[6] / INT[6] / N2HET2[4] / EPWM1B 12 Pulldown Enhanced PWM1 Output B
N2HET1[16] / EPWM1SYNCI / EPWM1SYNCO 97 Input Pulldown Fixed, 20 µA External ePWM Sync Pulse Input
N2HET1[16] / EPWM1SYNCI / EPWM1SYNCO 97 Output Pulldown – External ePWM Sync Pulse Output
GIOA[7] / INT[7] / N2HET2[6] / EPWM2A 18 Enhanced PWM2 Output A
N2HET1[0] / SPI4CLK / EPWM2B 19 Enhanced PWM2 Output B
N2HET1[2] / SPI4SIMO / EPWM3A 22 Enhanced PWM3 Output A
N2HET1[4] / EPWM4B 25 Enhanced PWM4 Output B
N2HET1[6] / SCIRX / EPWM5A 26 Enhanced PWM5 Output A
N2HET1[18] / EPWM6A 98 Enhanced PWM6 Output A
N2HET1[10] / nTZ3 83 Input Pulldown Trip Zone 1 input 3

4.2.2.5 General-Purpose Input/Output (GIO)

Table 4-24 PZ General-Purpose Input/Output (GIO)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 100 PZ
GIOA
GIOA[0] / INT[0] 1 I/O Pulldown Programmable, 20 µA General-purpose input/output
All GPIO terminals are capable of generating interrupts to the CPU on rising/falling/both edges.
GIOA[1] / INT[1] 2
GIOA[2] / INT[2] / N2HET2[0] / EQEP2I 5
GIOA[3] / INT[3] / N2HET2[2] 8
GIOA[4]/ INT[4] 9
GIOA[5] / INT[5] / EXTCLKIN / EPWM1A/ N2HET1_PIN_nDIS 10
GIOA[6] / INT[6] / N2HET2[4] / EPWM1B 12
GIOA[7] / INT[7] / N2HET2[6] / EPWM2A 18
GIOB
MIBSPI3nCS[0] / AD2EVT / GIOB[2] / EQEP1I/N2HET2_PIN_nDIS 38 I/O General-purpose input/output

4.2.2.6 Controller Area Network Interface Modules (DCAN1, DCAN2)

Table 4-25 PZ Controller Area Network Interface Modules (DCAN1, DCAN2)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 100 PZ
DCAN1
CAN1RX 63 I/O Pullup Programmable, 20 µA CAN1 Receive, or general-purpose I/O (GPIO)
CAN1TX 62 CAN1 Transmit, or GPIO
DCAN2
CAN2RX 92 I/O Pullup Programmable, 20 µA CAN2 Receive, or GPIO
CAN2TX 91 CAN2 Transmit, or GPIO

4.2.2.7 Standard Serial Peripheral Interfaces (SPI2 and SPI4)

Table 4-26 PZ Standard Serial Peripheral Interfaces (SPI2 and SPI4)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 100 PZ
SPI2
SPI2CLK 71 I/O Pullup Programmable, 20 µA SPI2 Serial Clock, or GPIO
SPI2nCS[0] 23 SPI2 Chip Select, or GPIO
SPI2SIMO 70 SPI2 Slave-In-Master-Out, or GPIO
SPI2SOMI 69 SPI2 Slave-Out-Master-In, or GPIO
The drive strengths for the SPI2CLK, SPI2SIMO and SPI2SOMI signals are selected individually by configuring the respective SRS bits of the SPIPC9 register fo SPI2.
SRS = 0 for 8mA drive (fast). This is the default mode as the SRS bits in the SPIPC9 register default to 0.
SRS = 1 for 2mA drive (slow)
SPI4
N2HET1[0] / SPI4CLK / EPWM2B 19 I/O Pulldown Programmable, 20 µA SPI2 Serial Clock, or GPIO
N2HET1[2] / SPI4SIMO / EPWM3A 22 SPI2 Slave-In-Master-Out, or GPIO

4.2.2.8 Multibuffered Serial Peripheral Interface (MibSPI1 and MibSPI3)

Table 4-27 PZ Multibuffered Serial Peripheral Interface (MibSPI1 and MibSPI3)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 100 PZ
MibSPI1
MIBSPI1CLK 67 I/O Pullup Programmable, 20 µA MibSPI1 Serial Clock, or GPIO
MIBSPI1nCS[0]/MIBSPI1SOMI[1]/
ECAP6		 73 MibSPI1 Chip Select, or GPIO
MIBSPI1nCS[1]/N2HET1[17]/
EQEP1S		 93
MIBSPI1nCS[2]/N2HET1[19] 27
MIBSPI1nCS[3]/N2HET1[21] 39
MIBSPI1nENA/N2HET1[23]/
ECAP4		 68 MibSPI1 Enable, or GPIO
MIBSPI1SIMO[0] 65 MibSPI1 Slave-In-Master-Out, or GPIO
N2HET1[8]/MIBSPI1SIMO[1] 74
MIBSPI1SOMI[0] 66 MibSPI1 Slave-Out-Master-In, or GPIO
MIBSPI1nCS[0]/MIBSPI1SOMI[1]/
ECAP6		 73
MibSPI3
MIBSPI3CLK/AWM1_EXT_SEL[1]/
EQEP1A		 36 I/O Pullup Programmable, 20 µA MibSPI3 Serial Clock, or GPIO
MIBSPI3nCS[0]/AD2EVT/GIOB[2]/
EQEP1I/N2HET2_PIN_nDIS		 38 MibSPI3 Chip Select, or GPIO
MIBSPI3nENA/MIBSPI3nCS[5]/
N2HET1[31]/EQEP1B		 37
MIBSPI3nENA/MIBSPI3nCS[5]/
N2HET1[31]/EQEP1B		 37 MibSPI3 Enable, or GPIO
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/
ECAP3		 35 MibSPI3 Slave-In-Master-Out, or GPIO
MIBSPI3SOMI[0]/AWM1_EXT_ENA/
ECAP2		 34 MibSPI3 Slave-Out-Master-In, or GPIO

4.2.2.9 Local Interconnect Network Controller (LIN)

Table 4-28 PZ Local Interconnect Network Controller (LIN)

TERMINAL SIGNAL TYPE RESET PULL STATE PULL TYPE DESCRIPTION
SIGNAL NAME 100 PZ
LINRX 94 I/O Pullup Programmable, 20 µA LIN Receive, or GPIO
LINTX 95 LIN Transmit, or GPIO

4.2.2.10 Multibuffered Analog-to-Digital Converter (MibADC)

Table 4-29 PZ Multibuffered Analog-to-Digital Converter (MibADC)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 100 PZ
MibADC1
AD1EVT 58 I/O Pulldown Programmable, 20 µA ADC1 Event Trigger or GPIO
AD1IN[0] 42 Input – – Analog Inputs
AD1IN[1] 49
AD1IN[2] 51
AD1IN[3] 52
AD1IN[4] 54
AD1IN[5] 55
AD1IN[6] 56
AD1IN[7] 43
AD1IN[8]/AD2IN[8] 57
AD1IN[9]/AD2IN[9] 48
AD1IN[10]/AD2IN[10] 50
AD1IN[11]/AD2IN[11] 53
AD1IN[16]/AD2IN[0] 40
AD1IN[17]/AD2IN[1] 41
AD1IN[20]/AD2IN[4] 44
AD1IN[21]/AD2IN[5] 45
ADREFHI/VCCAD 46 Input/
Power		 – – ADC High Reference Level/ADC Operating Supply
ADREFLO/VSSAD 47 Input/
Ground		 – – ADC Low Reference Level/ADC Supply Ground
MIBSPI3SOMI[0]/AWM1_EXT_ENA/
ECAP2		 34 AWM external analog mux enable
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/
ECAP3		 35 AWM external analog mux select line 0
MIBSPI3CLK/AWM1_EXT_SEL[1]/
EQEP1A		 36 AWM external analog mux select line1
MibADC2
MIBSPI3nCS[0]/AD2EVT/GIOB[2]/
EQEP1I/N2HET2_PIN_nDIS		 38 I/O ADC2 Event Trigger or GPIO

4.2.2.11 System Module Interface

Table 4-30 PZ System Module Interface

TERMINAL SIGNAL TYPE RESET
PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 100 PZ
nPORRST 31 Input Pullup 100 µA Power-on reset, cold reset External power supply monitor circuitry must drive nPORRST low when any of the supplies to the microcontroller fall out of the specified range. This terminal has a glitch filter. See Section 6.8.
nRST 81 I/O Pullup 100 µA The external circuitry can assert a system reset by driving nRST low. To ensure that an external reset is not arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal. This terminal has a glitch filter. See Section 6.8.
nERROR 82 I/O Pulldown 20 µA ESM Error Signal. Indicates error of high severity. See Section 6.8.

4.2.2.12 Clock Inputs and Outputs

Table 4-31 PZ Clock Inputs and Outputs

TERMINAL SIGNAL TYPE RESET PULL STATE PULL TYPE DESCRIPTION
SIGNAL NAME 100 PZ
OSCIN 14 Input – – From external crystal/resonator, or external clock input
KELVIN_GND 15 Input – – Dedicated ground for oscillator
OSCOUT 16 Output – – To external crystal/resonator
ECLK 84 I/O Pulldown Programmable, 20 µA External prescaled clock output, or GIO.
GIOA[5]/INT[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS 10 Input Pulldown 20 µA External Clock In

4.2.2.13 Test and Debug Modules Interface

Table 4-32 PZ Test and Debug Modules Interface

TERMINAL SIGNAL TYPE RESET PULL STATE PULL TYPE DESCRIPTION
SIGNAL NAME 100 PZ
nTRST 76 Input Pulldown Fixed, 100 µA JTAG test hardware reset
RTCK 80 Output – – JTAG return test clock
TCK 79 Input Pulldown Fixed, 100 µA JTAG test clock
TDI 77 I/O Pullup Fixed, 100 µA JTAG test data in
TDO 78 I/O Pulldown Fixed, 100 µA JTAG test data out
TMS 75 I/O Pullup Fixed, 100 µA JTAG test select
TEST 24 I/O Pulldown Fixed, 100 µA Test enable. This terminal must be connected to ground directly or via a pulldown resistor.

4.2.2.14 Flash Supply and Test Pads

Table 4-33 PZ Flash Supply and Test Pads

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 100 PZ
VCCP 96 3.3-V Power – – Flash external pump voltage (3.3 V). This terminal is required for both Flash read and Flash program and erase operations.
FLTP1 3 Input – – Flash Test Pins. For proper operation this terminal must connect only to a test pad or not be connected at all [no connect (NC)].
The test pad must not be exposed in the final product where it might be subjected to an ESD event.
FLTP2 4 Input – –

4.2.2.15 Supply for Core Logic: 1.2-V Nominal

Table 4-34 PZ Supply for Core Logic: 1.2-V Nominal

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 100 PZ
VCC 13 1.2-V Power – – Digital logic and RAM supply
VCC 21
VCC 30
VCC 32
VCC 61
VCC 88
VCC 99

4.2.2.16 Supply for I/O Cells: 3.3-V Nominal

Table 4-35 PZ Supply for I/O Cells: 3.3-V Nominal

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 100 PZ
VCCIO 6 3.3-V Power – – I/O Supply
VCCIO 28
VCCIO 60
VCCIO 85

4.2.2.17 Ground Reference for All Supplies Except VCCAD

Table 4-36 PZ Ground Reference for All Supplies Except VCCAD

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 100 PZ
VSS 7 Ground – – Device Ground Reference. This is a single ground reference for all supplies except for the ADC Supply.
VSS 17
VSS 20
VSS 29
VSS 33
VSS 59
VSS 72
VSS 86
VSS 87
VSS 100

4.3 Pin Multiplexing

This microcontroller has several interfaces and uses extensive multiplexing to bring out the functions as required by the target application. The multiplexing is mostly on the output signals. A few inputs are also multiplexed to allow the same input signal to be driven in from a selected terminal.

4.3.1 Output Multiplexing

Table 4-37 and Table 4-38 show the pin multiplexing control x register (PINMMRx) and the associated bit fields that control each pin mux function.


Table 4-37 Multiplexing for Outputs on 144-Pin PGE Package(1)

144-PIN
PGE 		DEFAULT
FUNCTION		 CTRL1 OPTION 2 CTRL2 OPTION 3 CTRL3 OPTION 4 CTRL4 OPTION 5 CTRL5 OPTION 6 CTRL6
86 AD1EVT 10[0]
2 GIOA[0] 0[8]
5 GIOA[1] 1[0]
9 GIOA[2] 2[0] N2HET2[0] 2[3] EQEP2I 2[4]
14 GIOA[5] 2[24] EXTCLKIN1 2[25] EPWM1A 2[26]
16 GIOA[6] 3[16] N2HET2[4] 3[17] EPWM1B 3[18]
22 GIOA[7] 4[0] N2HET2[6] 4[1] EPWM2A 4[2]
126 GIOB[0] 18[24]
133 GIOB[1] 21[8]
1 GIOB[3] 0[0]
105 MIBSPI1NCS[0] 13[24] MIBSPI1SOMI[1] 13[25] ECAP6 13[28]
130 MIBSPI1NCS[1] 20[16] N2HET1[17] 20[17] EQEP1S 20[20]
40 MIBSPI1NCS[2] 8[8] N2HET1[19] 8[9]
96 MIBSPI1NENA 12[16] N2HET1[23] 12[17] ECAP4 12[20]
53 MIBSPI3CLK 33[24] AWM1_EXT_SEL[1] 33[25] EQEP1A 33[26]
55 MIBSPI3NCS[0] 9[16] AD2EVT 9[17] GIOB[2] 9[18] EQEP1I 9[19]
37 MIBSPI3NCS[1] 7[8] N2HET1[25] 7[9]
4 MIBSPI3NCS[2] 0[24] I2C_SDA 0[25] N2HET1[27] 0[26] nTZ2 0[27]
3 MIBSPI3NCS[3] 0[16] I2C_SCL 0[17] N2HET1[29] 0[18] nTZ1 0[19]
54 MIBSPI3NENA 9[8] MIBSPI3NCS[5] 9[9] N2HET1[31] 9[10] EQEP1B 9[11]
52 MIBSPI3SIMO 33[16] AWM1_EXT_SEL[0] 33[17] ECAP3 33[18]
51 MIBSPI3SOMI 33[8] AWM1_EXT_ENA 33[9] ECAP2 33[10]
100 MIBSPI5CLK 13[16]
32 MIBSPI5NCS[0] 27[0] EPWM4A 27[2]
97 MIBSPI5NENA 12[24] MIBSPI5SOMI[1] 12[28] ECAP5 12[29]
99 MIBSPI5SIMO[0] 13[8] MIBSPI5SOMI[2] 13[12]
98 MIBSPI5SOMI[0] 13[0]
25 N2HET1[0] 5[0] SPI4CLK 5[1] EPWM2B 5[2]
23 N2HET1[01] 4[16] SPI4NENA 4[17] 4[19] N2HET2[8] 4[20] EQEP2A 4[21]
30 N2HET1[02] 5[8] SPI4SIMO 5[9] EPWM3A 5[10]
24 N2HET1[03] 4[24] SPI4NCS[0] 4[25] 4[27] N2HET2[10] 4[28] EQEP2B 4[29]
36 N2HET1[04] 33[0] EPWM4B 33[1]
31 N2HET1[05] 5[16] SPI4SOMI 5[17] N2HET2[12] 5[18] EPWM3B 5[19]
38 N2HET1[06] 7[16] SCIRX 7[17] EPWM5A 7[18]
33 N2HET1[07] 6[0] N2HET2[14] 6[3] EPWM7B 6[4]
106 N2HET1[08] 14[0] MIBSPI1SIMO[1] 14[1]
35 N2HET1[09] 6[16] N2HET2[16] 6[17] EPWM7A 6[20]
118 N2HET1[10] 17[0] nTZ3 17[4]
6 N2HET1[11] 1[8] MIBSPI3NCS[4] 1[9] N2HET2[18] 1[10] EPWM1SYNCO 1[13]
124 N2HET1[12] 17[16]
39 N2HET1[13] 8[0] SCITX 8[1] EPWM5B 8[2]
125 N2HET1[14] 18[8]
41 N2HET1[15] 8[16] MIBSPI1NCS[4] 8[17] ECAP1 8[18]
139 N2HET1[16] 34[0] EPWM1SYNCI 34[1] EPWM1SYNCO 34[2]
140 N2HET1[18] 34[8] EPWM6A 34[9]
141 N2HET1[20] 34[16] EPWM6B 34[17]
15 N2HET1[22] 3[8]
91 N2HET1[24] 11[24] MIBSPI1NCS[5] 11[25]
92 N2HET1[26] 12[0]
107 N2HET1[28] 14[8]
127 N2HET1[30] 19[8] EQEP2S 19[11]
  1. The CTRLx columns contain a value of type x[y], which indicates the pin multiplexing control x register (PINMMRx) and the associated bit field [y].

Table 4-38 Multiplexing for Outputs on 100-Pin PZ Package(1)

100-PIN
PZ		 DEFAULT
FUNCTION		 CTRL1 OPTION 2 CTRL2 OPTION 3 CTRL3 OPTION 4 CTRL4 OPTION 5 CTRL5 OPTION 6 CTRL6
2 GIOA[1]/INT[1] 1[0]
5 GIOA[2]/INT[2] 2[0] N2HET2[0] 2[3] EQEP2I 2[4]
10 GIOA[5]/INT[5] 2[24] EXTCLKIN1 2[25] EPWM1A 2[26]
12 GIOA[6]/INT[6] 3[16] N2HET2[4] 3[17] EPWM1B 3[18]
18 GIOA[7]/INT[7] 4[0] N2HET2[6] 4[1] EPWM2A 4[2]
73 MIBSPI1NCS[0] 13[24] MIBSPI1SOMI[1] 13[25] ECAP6 13[28]
93 MIBSPI1NCS[1] 20[16] N2HET1[17] 20[17] EQEP1S 20[20]
27 MIBSPI1NCS[2] 8[8] N2HET1[19] 8[9]
68 MIBSPI1NENA 12[16] N2HET1[23] 12[17] ECAP4 12[20]
36 MIBSPI3CLK 33[24] AWM1_EXT_SEL[1] 33[25] EQEP1A 33[26]
38 MIBSPI3NCS[0] 9[16] AD2EVT 9[17] GIOB[2] 9[18] EQEP1I 9[19]
37 MIBSPI3NENA 9[8] MIBSPI3NCS[5] 9[9] N2HET1[31] 9[10] EQEP1B 9[11]
35 MIBSPI3SIMO[0] 33[16] AWM1_EXT_SEL[0] 33[17] ECAP3 33[18]
34 MIBSPI3SOMI[0] 33[8] AWM1_EXT_ENA 33[9] ECAP2 33[10]
19 N2HET1[0] 5[0] SPI4CLK 5[1] EPWM2B 5[2]
22 N2HET1[02] 5[8] SPI4SIMO 5[9] EPWM3A 5[10]
25 N2HET1[04] 33[0] EPWM4B 33[1]
26 N2HET1[06] 7[16] SCIRX 7[17] EPWM5A 7[18]
74 N2HET1[08] 14[0] MIBSPI1SIMO[1] 14[1]
83 N2HET1[10] 17[0] nTZ3 17[4]
97 N2HET1[16] 34[0] EPWM1SYNCI 34[1] EPWM1SYNCO 34[2]
98 N2HET1[18] 34[8] EPWM6A 34[9]
64 N2HET1[24] 11[24] MIBSPI1NCS[5] 11[25]
(1) The CTRLx columns contain a value of type x[y], which indicates the pin multiplexing control x register (PINMMRx) and the associated bit field [y].

4.3.2 Multiplexing of Inputs

Some signals are connected to more than one terminal, the inputs for these signals can come from any of the terminals. A multiplexor is implemented to let the application choose the terminal that will be used, providing the input signal is from among the available options.

Table 4-39 Input Multiplexing and Control for All Packages [144-Pin PGE, and 100-Pin PZ](1)

SIGNAL
NAME		 DEDICATED INPUTS MULTIPLEXED INPUTS INPUT MULTIPLEXOR
CONTROL		 INPUT PATH SELECTED
144 PGE 100 PZ 144 PGE 100 PZ BIT1 BIT2 DEDICATED, IF MUXED, IF
GIOB[2] 142 – 55 38 PINMUX29[16] PINMUX29[16] BIT1 = 0(3) BIT1 = 1(3)
N2HET1[17] – – 130 93 PINMUX20[17] PINMUX24[16] not(BIT1) or (BIT1 and BIT2) = 1 BIT1 and not(BIT2) = 1
N2HET1[19] – – 40 27 PINMUX8[9] PINMUX24[24] not(BIT1) or (BIT1 and BIT2) = 1 BIT1 and not(BIT2) = 1
N2HET1[21] – – – – PINMUX9[25] PINMUX25[0] not(BIT1) or (BIT1 and BIT2) = 1 BIT1 and not(BIT2) = 1
N2HET1[23] – – 96 68 PINMUX12[17] PINMUX25[8] not(BIT1) or (BIT1 and BIT2) = 1 BIT1 and not(BIT2) = 1
N2HET1[25] – – 37 – PINMUX7[9] PINMUX25[16] not(BIT1) or (BIT1 and BIT2) = 1 BIT1 and not(BIT2) = 1
N2HET1[27] – – 4 – PINMUX0[26] PINMUX25[24] not(BIT1) or (BIT1 and BIT2) = 1 BIT1 and not(BIT2) = 1
N2HET1[29] – – 3 – PINMUX0[18] PINMUX26[0] not(BIT1) or (BIT1 and BIT2) = 1 BIT1 and not(BIT2) = 1
N2HET1[31] – – 54 37 PINMUX9[10] PINMUX26[8] not(BIT1) or (BIT1 and BIT2) = 1 BIT1 and not(BIT2) = 1
  1. The default inputs to the modules are from the dedicated input terminals. The application must configure the PINMUX registers as shown in order to select the multiplexed input path, if required.
  2. The SPI4CLK, SPI4SIMO, SPI4SOMI, SPI4nENA and SPI4nCS[0] signals do not have a dedicated signal pad on this device. Therefore, the input multiplexors on these inputs are not required. The control registers are still available to maintain compatibility to the emulation device.
  3. When the muxed input is selected for GIOB[2], the PINMUX9[16] and PINMUX9[17] must be cleared. These bits affect the control over the PULDIS (pull disable) and PSEL (pull select). When the multiplexed input path is selected for GIOB[2], the PULDIS is tied to 0 (pull is enabled, cannot be disabled) and the PULSEL is tied to 1 (pull up selected, not programmable).

4.4 Buffer Type

Table 4-40 Output Buffer Drive Strengths

Low-level Output Current, IOL for VI = VOLmax
or
High-level Output Current, IOH for VI = VOHmin		 Signals
8mA

MIBSPI5CLK, MIBSPI5SOMI[0], MIBSPI5SOMI[1], MIBSPI5SOMI[2], MIBSPI5SOMI[3], MIBSPI5SIMO[0], MIBSPI5SIMO[1], MIBSPI5SIMO[2], MIBSPI5SIMO[3],

TMS, TDI, TDO, RTCK,

SPI4CLK, SPI4SIMO, SPI4SOMI, SPI4NCS[0], SPI4NENA, nERROR,

N2HET2[1], N2HET2[3], N2HET2[5], N2HET2[7], N2HET2[9], N2HET2[11], N2HET2[13], N2HET2[15]

ECAP1, ECAP4, ECAP5, ECAP6

EQEP1I, EQEP1S, EQEP2I, EQEP2S

EPWM1A, EPWM1B, EPWM1SYNCO, EPW2A, EPWM2B, EPWM3A, EPWM3B, EPWM4A, EPWM4B, EPWM5A, EPWM5B, EPWM6A, EPWM6B, EPWM7A, EPWM7B
4mA

TEST,

MIBSPI3SOMI, MIBSPI3SIMO, MIBSPI3CLK, MIBSPI1SIMO, MIBSPI1SOMI, MIBSPI1CLK,

ECAP2, ECAP3

nRST
2mA zero-dominant

AD1EVT,

CAN1RX, CAN1TX, CAN2RX, CAN2TX, CAN3RX, CAN3TX,

GIOA[0-7], GIOB[0-7],

LINRX, LINTX,

MIBSPI1NCS[0], MIBSPI1NCS[1-3], MIBSPI1NENA, MIBSPI3NCS[0-3], MIBSPI3NENA, MIBSPI5NCS[0-3], MIBSPI5NENA,

N2HET1[0-31], N2HET2[0], N2HET2[2], N2HET2[4], N2HET2[6], N2HET2[8], N2HET2[10], N2HET2[12], N2HET2[14], N2HET2[16], N2HET2[18],

selectable 8mA / 2mA

ECLK,

SPI2CLK, SPI2SIMO, SPI2SOMI

The default output buffer drive strength is 8mA for these signals.

Table 4-41 Selectable 8mA/2mA Control

SIGNAL CONTROL BIT ADDRESS 8mA (DEFAULT) 2mA
ECLK SYSPC10[0] 0xFFFF FF78 0 1
SPI2CLK SPI2PC9[9] 0xFFF7 F668 0 1
SPI2SIMO SPI2PC9[10] 0xFFF7 F668 0 1
SPI2SOMI SPI2PC9[11](1) 0xFFF7 F668 0 1
(1) Either SPI2PC9[11] or SPI2PC9[24] can change the output strength of the SPI2SOMI pin. In case of a 32-bit write where these two bits differ, SPI2PC9[11] determines the drive strength.
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